Semiconductor device and method for driving the same

ABSTRACT

A semiconductor device includes: a control-voltage supply unit  110;  an MOS transistor including a gate electrode  109  and drain and source regions  103   a  and  103   b;  a dielectric capacitor  104;  and a resistor  106.  The dielectric capacitor  104  and the resistor  106  are disposed in parallel and interposed between the gate electrode  109  and the control-voltage supply unit  110.  With this structure, a charge is accumulated in each of an intermediate electrode of the dielectric capacitor  104  and the gate electrode  109  upon the application of a voltage, thereby varying a threshold value of the MOS transistor. In this manner, the history of input signals can be stored as a variation in a drain current in the MOS transistor, thus allowing multilevel information to be held.

[0001] This is a continuation of Application PCT/JP02/06250, filed Jun.21, 2002, now abandoned.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to semiconductor devices andmethods for driving the same. More particularly, the present inventionrelates to semiconductor devices which are applicable to neural networkcomputers (neurocomputers), for example, and allows multilevelinformation to be stored therein, and also relates to methods fordriving the devices.

[0003] As multimedia has been developed, semiconductor devices are moreand more required to improve their performance. For example, to processa large capacity of digital information, even CPUs of personal computersoperating at high speeds of 1 GHz or more have come onto the market.

[0004] To meet such a demand for improving the performance ofsemiconductor devices, semiconductor fabricators have improved theperformance mainly with techniques of downsizing the semiconductordevices.

[0005] However, even physical limitations are now pointed out indownsizing the semiconductor devices, and therefore, improvement in thesemiconductor devices by further downsizing is not expected inconsideration of fabrication cost.

[0006] To solve this problem, in place of digital information processingtechniques to date that perform computations using a binary signal of“1” or “0”, multilevel cell technologies for converting information intothree or four levels, technologies for computers (neurocomputers) thatperform computation by mimicking the behavior of the brain of an animalwith the application of the multilevel cell technologies, and the like,have been researched.

[0007] The brain of an animal is basically composed of nerve cells,which are called neurons and have a computing function, and nervefibers, each of which transmits a computing result of a neuron toanother neuron, i.e., serves as so-called wiring.

[0008] A neurocomputer is composed of a large number of neuron units,which are made of semiconductor elements corresponding to neurons, and alarge number of synapse units, which transmits signals to the neuronunits and add weights to the signals. Combinations of the neuron unitsand the synapse units are hereinafter referred to as neuron elements.

[0009] When information signals having different “weights” and beingoutput from a plurality of previous-stage neuron elements are input to aneuron element, the information signals are added to this neuronelement. When the sum of the information signals exceeds a thresholdvalue, the neuron element “fires” to allow a signal to be output to asubsequent-stage neuron element. Information is processed by repeatingthis operation.

[0010] A process by which the brain of an animal learns is considered aprocess of varying weights on synaptic connections. That is to say, theweights are gradually modified with respect to various input signals soas to obtain an appropriate output, and finally the weights stay atappropriate values.

[0011] To configure a neural network having such a leaning function, itis necessary to vary the strength on each synaptic connection asrequired and to store the varied strength. Therefore, the multilevelcell technologies have become essential for implementing neurocomputers.

[0012] The neurocomputer described above is an example of application ofthe multilevel cell technologies. Naturally, multilevel memories inwhich multilevel information is stored therein with stability have beenresearched actively. As is evident from these factors, the multilevelcell technologies for information have become extremely important forfuture semiconductor devices.

[0013] As an example of such multilevel cell technologies, a knowntechnique for allowing information with at least three levels to bestored in a single memory cell was disclosed in Japanese Laid-OpenPublication No. 8-124378.

[0014]FIG. 49 is a cross-sectional view showing a known semiconductordevice functioning as a multilevel memory. As shown in FIG. 49, theknown semiconductor device includes: a silicon substrate 1107; welllines BUL1 and BUL2 buried in the silicon substrate 1107; PZT films 1109made of a ferroelectric and formed on the well lines BUL1 and BUL2,respectively; a word line WL1 formed on the PZT films 1109; a bit lineBL1 formed over the word line WL1 and the well line BUL1; and a bit lineBL2 formed over the word line WL1 and the well line BUL2. Although notshown, source and drain are provided in each of the well lines BUL1 andBUL2. The bit line BL1 is connected to the drain in the well line BUL1via a bit contact (not shown), while the bit line BL2 is connected tothe drain in the well line BUL2 via a bit contact.

[0015] Information is written by changing the polarization in the PZTfilm 1109 upon the application of a voltage to the word line WL1 and thewell lines BUL1 and BUL2.

[0016]FIG. 50 is a graph showing a relationship between a voltage VGBapplied to the gate electrode (=the potential at the gate electrode-thepotential at the well) and the magnitude of the polarization of theferroelectric (i.e., hysteresis characteristics) in each memory cell ofthe known device. Since the ferroelectric has hysteresischaracteristics, the polarization state changes depending on the historyof the applied voltage, and even after the voltage has been removed, thepolarization state remains as indicated by a point A, B or C in FIG. 50.If a voltage V=V₁ at which the ferroelectric is in a saturatedpolarization state is applied and then removed, the polarization is atthe point A. When a voltage is removed after the application of avoltage V=−V₂, the polarization is at the point C. If a voltage V=−V₁ isapplied and then removed, the polarization is at the point B.

[0017]FIG. 51 is a graph showing the relationship between a draincurrent I and a gate voltage VGB in a memory cell when the ferroelectricis in the state indicated by the point A, C or B in FIG. 50. In FIG. 51,the left-side curve, the middle curve and the right-side curvecorrespond to the states indicated by the points A, C and B,respectively. In the state indicated by the point A, the ferroelectricexhibits a large positive polarization, so that a threshold voltage VtAof the memory cell is lower than a threshold voltage VtC in the stateindicated by the point C at which no polarization is exhibited. In thestate indicated by the point B, the ferroelectric exhibits a largenegative polarization, so that a threshold voltage VtB of the memorycell is higher than the threshold voltage VtC in the state indicated bythe point C at which no polarization is exhibited. By thus providing theferroelectric with the three polarization states indicated by the pointA, C and B, the memory cell can be controlled to have three differentlevels of threshold voltages. Therefore, it is possible to storeinformation with three levels in the memory cell corresponding to thevalues of these threshold voltages. The known technique described aboveindicates that if a polarization state between the points A and C isused, the number of levels can be further increased.

[0018] However, the known technique has a basic problem that thepolarization state “C” is difficult to obtain accurately. Specifically,in the known technique, when a voltage is removed after theferroelectric has exhibited a small polarization upon the application ofan appropriate voltage, the polarization comes close to zero. However,as shown in FIG. 50, the hysteresis of the ferroelectric changes greatlyin the vicinity of a coercive voltage Vc, while the absolute value ofthe voltage −V₂ is essentially close to the coercive voltage Vc. Thus,the polarization of the ferroelectric is extremely difficult to control,resulting in that the polarization value after the removal of thevoltage changes greatly only by a small variation in the voltage V₂caused by noise or the like. In addition to such a variation in thewrite voltage, variations in the crystal state and the thickness of theferroelectric, for example, also vary the coercive voltage Vc. Thisresults in difficulty in obtaining stable multilevel storage propertieswith high reliability and excellent reproducibility. The coercivevoltage herein refers to a voltage required for changing the hysteresisof the ferroelectric largely to alter the distribution of the charge ina ferroelectric capacitor.

SUMMARY OF THE INVENTION

[0019] An object of the present invention is providing a highly reliablesemiconductor device in which information can be stored with stabilityand which is applicable as a neuron element for a neurocomputer and amethod for driving the semiconductor device.

[0020] A first semiconductor device of the present invention includes: asemiconductor substrate; and a memory in which a first capacitor,including a first upper electrode, a first dielectric layer and a firstlower electrode and formed over the semiconductor substrate, and asecond capacitor, including a second upper electrode, a seconddielectric layer and a second lower electrode and formed over thesemiconductor substrate, are disposed. The semiconductor device canstore information with three or more levels. The first and seconddielectric layers have hysteresis characteristics exhibiting mutuallydiffering coercive voltages.

[0021] In this device, a metastable point is created on a hysteresisloop of the whole of the capacitors, thus allowing information withthree or more levels to be stored with stability even when a writevoltage varies.

[0022] The first and second capacitors may be polarized in one directionduring operation. Then, at least one metastable point is created on thehysteresis loop due to the difference in coercive voltage between thefirst and second capacitors. As a result, information with three or morelevels can be stored with stability.

[0023] The semiconductor device may further include a transistorincluding: a gate insulating film formed on the semiconductor substrate;and a gate electrode formed on the gate insulating film and made of aconductor film. Both of the first and second lower electrodes may beunited with the gate electrode. Then, the number of process steps forfabricating a semiconductor device in which multilevel information canbe stored with stability is reduced, thus reducing the fabrication cost.

[0024] The semiconductor device may further include: a gate insulatingfilm formed on the semiconductor substrate; and a gate electrode formedon the gate insulating film and made of a conductor film. Each of thefirst and second lower electrodes may be connected to the gateelectrode. Then, a voltage applied to the capacitors is transmitted tothe gate electrode so that a drain current flowing upon the applicationof the gate voltage is varied depending on the state of the memory. As aresult, multilevel information can be stored with stability.

[0025] In respective first-half stages in ranges in which thepolarizations of the first and second capacitors are from zero tosaturation, the polarizations of the first and second capacitors mayvary at mutually different rates with change in voltage. Then, ametastable point can be created on the hysteresis loop of the whole ofthe capacitors as intended. That is to say, the storing operation isperformed with stability even when the write voltage is varied by noiseor the like.

[0026] Each of the first and second dielectric layers may include aferroelectric layer. Then, polarization states corresponding to multiplelevels are created depending on a remanent polarization after theapplication of the voltage to the capacitors, thus allowing a multilevelstoring operation.

[0027] The first and second upper electrodes may be connected to eachother. Then, write voltages can be applied using an identical line.

[0028] The first and second dielectric layers are preferably formed outof an identical film. Then, the area of the memory can be reduced, ascompared to the case where the first and second dielectric layers areseparately formed. In addition, the number of fabricating process stepscan be also reduced.

[0029] The first and second dielectric layers are preferably made of anidentical material, and the semiconductor device may further include aparaelectric capacitor connected in parallel with the first and secondcapacitors.

[0030] The semiconductor device preferably includes a capacitorinterposed between the second capacitor and the gate electrode. Then, anapparent coercive voltage of the second capacitor can be varied, thusfurther enhancing the flexibility in designing.

[0031] The first and second dielectric layers may differ mutually inarea. Then, the coercive voltages of the capacitors can be varied.

[0032] The first and second dielectric layers may be made of mutuallydifferent materials. Then, the first and second capacitors can be formedto have mutually different coercive voltages.

[0033] The first and second dielectric layers may differ mutually inthickness. Then, the first and second capacitors can be formed to havemutually different coercive voltages.

[0034] The area ratio between the electrodes of the first and secondcapacitors, i.e., (the area of the first capacitor)/(the area of thesecond capacitor), is in the range of 0.2 to 2, both inclusive. Then, ifthe first and second dielectric layers are made of an identicalmaterial, separation of stored information is excellent, resulting thatinformation with three levels can be held with stability.

[0035] In particular, the area ratio between the electrodes of the firstand second capacitors, i.e., (the area of the first capacitor)/(the areaof the second capacitor), is in the range of 0.5 to 2, both inclusive.Then, separation of stored information is excellent, resulting that eveninformation with four or more levels can be held with stability in thesemiconductor device.

[0036] A second semiconductor device of the present invention includes:a control-voltage supply unit; a field-effect transistor including agate electrode having a function of accumulating a charge; and acapacitor and a resistor, disposed in parallel and interposed betweenthe control-voltage supply unit and the gate electrode. Thesemiconductor device can store multilevel information.

[0037] In this device, current flows through the resistor upon theapplication of a write voltage to the resistor, so that a charge isaccumulated in the gate electrode to vary the threshold value of thefield-effect transistor. In addition, the field-effect transistor has aplurality of states which are held for a given period, so thatmultilevel information can be stored. Furthermore, the information isread out according to the variation in a drain current in thefield-effect transistor. Thus, the semiconductor device is usable notonly as a multilevel memory but also as an element for assigning weightsto signals in a neurocomputer.

[0038] A charge may be injected from the control-voltage supply unitinto the gate electrode. Then a charge can be injected in a mannerdifferent from that in a flash memory.

[0039] The semiconductor device may function as an analog memory inwhich multilevel information can be stored continuously according to theamount of the charge accumulated in the gate electrode. Then, the deviceis usable for various purposes such as weighing in a neurocomputer, ascompared to a flash memory, for example.

[0040] The resistor may be made of a dielectric material. Then, thecharge accumulated in the gate electrode is unlikely to leak. Thus,input information can be held for a longer period than in the case wherethe resistor is made of undoped silicon, for example. In addition, sincethe resistor can be formed on the transistor, the cell size can bereduced.

[0041] The control-voltage supply unit may be as an upper electrode. Thegate electrode of the field-effect transistor may be connected to anintermediate electrode. The capacitor may be a dielectric capacitorincluding the upper electrode, the intermediate electrode and adielectric layer interposed between the upper electrode and theintermediate electrode. The dielectric layer may have a resistancecomponent functioning as the resistor. For example, the dielectric layerof the dielectric capacitor and the resistor may be one and the same. Insuch a case, the area of the device is reduced, as compared to the casewhere the resistor and the dielectric layer are separately provided.

[0042] The resistor preferably has a resistance value that variesaccording to the strength of an electric field applied to the resistor.Then, the amount of the charge accumulated in the gate electrode can beadjusted.

[0043] The resistor preferably has a resistance value which is almostconstant when the strength of an electric field applied to the resistoris at a level equal to or smaller than a given level and which decreaseswhen the strength of the electric field exceeds the given level. Then,the device can be driven by a plurality of methods, e.g., byaccumulating a charge in the gate electrode in a short time by applyingan electric field exceeding a given value or by accumulating a chargefor a relatively long time by applying an electric field not higher thanthe given value.

[0044] A pass current flowing through the resistor preferably increasessubstantially in proportion to a voltage applied to both ends of theresistor when the absolute value of the applied voltage is equal to orsmaller than a given value, while the pass current preferably increasesexponentially when the absolute value of the applied voltage exceeds thegiven value. Then, the device can be driven by a plurality of methods asdescribed above.

[0045] A pass current flowing per unit area of the resistor ispreferably 100 [mA/cm²] or less in a voltage range in which the passcurrent flowing through the resistor increases substantially inproportion to the voltage. Then, written information or the history ofthe written information can be held for a given period. The smaller thepass current is, the longer the holding time (the recovery time) of theinformation is required.

[0046] The capacitor may include a ferroelectric layer, and the resistormay be made of a ferroelectric material. Then, the amount of the chargeaccumulated in each of the intermediate electrode and the gate electrodecan be also varied depending on the polarization direction in theferroelectric layer. As a result, the semiconductor device of thepresent invention is usable as a multilevel memory with more levels thanin the case where a capacitor including a paraelectric layer is used. Inaddition, the inventive device is applicable as a neuron element withextremely high flexibility in weighting.

[0047] The semiconductor device preferably further includes at least oneresistor provided separately from the capacitor. Then, materials havingvarious properties are usable for the resistor, thereby easily ensuringa semiconductor device holding multilevel information more effectively.

[0048] The resistor provided separately from the capacitor is preferablya variable resistor that includes an oxide containing an elementselected from the group consisting of Ba, Sr, Ti, Zn, Fe and Cu, orincludes an element selected from the group consisting of SiC, Si andSe. Then, the following controls can be performed. That is to say, acharge is injected in the gate electrode in a voltage range in which theresistance value of the resistor is small, while the charge injection isfinely controlled in a voltage range in which the resistance value islarge.

[0049] The resistors are preferably diodes that are connected inparallel and disposed in opposite orientations.

[0050] The semiconductor device preferably further includes an MIStransistor which has an ON resistance functioning as the resistorprovided separately from the capacitor.

[0051] The resistor provided separately from the capacitor is preferablya variable resistance element made of a variable resistance materialhaving a resistance value that varies depending on the crystallinity ofthe material.

[0052] The semiconductor device is preferably used as a synapse unit ina neurocomputer. Then, a high-performance neurocomputer isimplementable.

[0053] An inventive method for driving a semiconductor device includinga control-voltage supply unit, a field-effect transistor including agate electrode having a function of accumulating a charge, a capacitor,and a resistor, the capacitor and the resistor being disposed inparallel and interposed between the control-voltage supply unit and thegate electrode, includes the steps of: a) applying a write voltage toboth ends of the resistor to vary the amount of the charge accumulatedin the gate electrode via the resistor, thereby changing a thresholdvoltage of the field-effect transistor; and b) reading out informationaccording to variation in a drain current in the field-effecttransistor.

[0054] According to this method, information written by applying avoltage to a capacitor and a resistor in the step a) is held for a giventime period. In addition, in the step b), multilevel informationaccording to a variation in a drain current in a field-effect transistorcan be read out. Thus, the semiconductor device of the present inventioncan be driven as a multilevel memory. If the semiconductor device of thepresent invention is applied to a neurocomputer, the device is usable asan element having a function of adding weights to input information.

[0055] The capacitor may include a dielectric layer. Then, the chargeaccumulated in the gate electrode is unlikely to leak. Therefore, inputinformation can be held for a longer time than in the case where theresistor is made of an undoped silicon having a smaller resistancevalue.

[0056] In the step a), a pass current flowing through the resistorpreferably increases substantially in proportion to the write voltagewhen the absolute value of the write voltage is equal to or smaller thana give value; and the pass current preferably increases exponentially asthe write voltage increases, when the absolute value of the writevoltage exceeds the given value. Then, the operation of writinginformation performed in a short time by applying a pulse voltageexceeding a given value, and the operation of writing information byapplying a voltage equal to or lower than the given voltage, can be usedproperly. In particular, in the case where the device is used as aneuron element, the threshold value of the field-effect transistor isvaried by applying a voltage exceeding a given voltage, therebyexecuting learning with a storing operation replayed at a relatively lowvoltage.

[0057] In the step a), when the absolute value of the write voltage isequal to or smaller than the given value, the amount of the chargeaccumulated in the gate electrode is preferably controlled depending onthe length of a time period over which the write voltage is applied.That is to say, multilevel information can be written by a relativelysimple manner.

[0058] In the step a), when the absolute value of the write voltage isequal to or smaller than the given value, a pass current flowing perunit area of the resistor is preferably 100 [mA/cm²] or less. Then, therecovery time of the semiconductor device, i.e., the holding time ofinformation, can be ensured for a given period of time or longer.

[0059] In the step a), when the absolute value of the write voltageexceeds the given value, the write voltage is preferably set to have anuniform pulse width and the amount of the charge accumulated in the gateelectrode is preferably controlled depending on the magnitude of theabsolute value of the write voltage. Thus, multilevel information can bewritten also depending on the magnitude of the absolute value of thewrite voltage. In this case, the time period required for writing can bereduced, thereby allowing information to be stored for a short time.

[0060] In the step a), when the absolute value of the write voltageexceeds the given value, the amount of the charge accumulated in thegate electrode is preferably subjected to a coarse control, and when theabsolute value of the write voltage is lower than the give value, theamount of the charge accumulated in the gate electrode is preferablysubjected to a fine control.

[0061] In the step a), the write voltage is preferably in positive- andnegative-voltage ranges that extend to an identical absolute value.Then, the drain current characteristic of the field-effect transistordiffers between the application of a positive voltage and theapplication of a negative voltage. As a result, a larger amount ofinformation can be stored in the semiconductor device, than in the caseof application of only a positive voltage.

BRIEF DESCRIPTION OF DRAWINGS

[0062]FIG. 1 is a top plan view showing a multilevel memory according toa first embodiment of the present invention.

[0063]FIG. 2 is a cross-sectional view of the multilevel memory of thefirst embodiment, taken along the line II-II in FIG. 1.

[0064]FIG. 3 is a cross-sectional view of the multilevel memory of thefirst embodiment, taken along the line III-III in FIG. 1.

[0065]FIGS. 4A through 4E are cross-sectional views showing respectiveprocess steps for fabricating the multilevel memory of the firstembodiment.

[0066]FIG. 5 is an equivalent circuit diagram showing the multilevelmemory of the first embodiment.

[0067]FIG. 6 is a graph showing a polarization-voltage hysteresischaracteristic (P-V characteristic) of a capacitor MFM1.

[0068]FIG. 7 is a graph showing a P-V characteristic of a capacitorMFM2.

[0069]FIG. 8 is a graph showing the P-V characteristics of thecapacitors MFM1 and MFM2 and a P-V characteristic of the whole of thecapacitors.

[0070]FIG. 9 is a graph showing a P-V characteristic of the whole ofthree capacitors.

[0071]FIG. 10 is a graph showing a voltage applied between an upper gateelectrode and a lower electrode and the effective polarizations offerroelectric capacitors in the multilevel memory of the firstembodiment.

[0072]FIG. 11 is a graph showing a gate voltage-drain currentcharacteristic with respect to respective write voltages in themultilevel of the first embodiment.

[0073]FIG. 12 is a graph for describing a correlation between swings inwrite voltage and shifts in polarization value in a known multilevelmemory.

[0074]FIG. 13 is a graph showing a portion A in FIG. 12 undermagnification for the known multilevel memory.

[0075]FIG. 14 is a graph for describing a correlation between swings inwrite voltage and shifts in polarization value in the multilevel memoryof the first embodiment.

[0076]FIG. 15 shows a portion B in FIG. 14 under magnification of themultilevel memory of the first embodiment.

[0077]FIGS. 16A through 16D are graphs showing effective polarizationvalues when the area of the capacitor MFM2 is changed with respect tothe capacitor MFM1 in the multilevel memory of the present invention.

[0078]FIGS. 17A through 17D are graphs showing effective polarizationvalues when the area of the capacitor MFM1 is changed with respect tothe capacitor MFM2 in the multilevel memory of the present invention.

[0079]FIG. 18 is a cross-sectional view showing a modified example ofthe multilevel memory of the first embodiment.

[0080]FIG. 19 is a cross-sectional view showing a structure of amultilevel memory according to a second embodiment of the presentinvention.

[0081]FIG. 20 is a circuit diagram schematically showing a multilevelmemory according to a third embodiment of the present invention.

[0082]FIG. 21 is an equivalent circuit diagram showing a multilevelmemory according a fourth embodiment of the present invention.

[0083]FIG. 22 is an equivalent circuit diagram showing a semiconductordevice according to a fifth embodiment of the present invention.

[0084]FIG. 23 is a top plan view showing the semiconductor device of thefifth embodiment.

[0085]FIG. 24 is a cross-sectional view showing the semiconductor deviceof the fifth embodiment, taken along the line XXIV-XXIV in FIG. 23.

[0086]FIG. 25 is a cross-sectional view showing the semiconductor deviceof the fifth embodiment, taken along the line XXV-XXV in FIG. 23.

[0087]FIGS. 26A through 26D are cross-sectional views showing respectiveprocess steps for fabricating the semiconductor device of the fifthembodiment.

[0088]FIG. 27 is a graph showing an applied voltage-pass currentcharacteristic of a dielectric capacitor used in the semiconductordevice of the fifth embodiment.

[0089]FIG. 28 is a graph showing an applied voltage-drain currentcharacteristic of the semiconductor device of the fifth embodiment.

[0090]FIG. 29 shows a correlation between a pass current flowing throughthe dielectric capacitor and a recovery time in the semiconductor deviceof the fifth embodiment.

[0091]FIG. 30 is a graph showing an applied voltage-drain currentcharacteristic of a dielectric capacitor used in a semiconductor deviceaccording to a sixth embodiment of the present invention.

[0092]FIG. 31 is a graph showing an applied voltage-drain currentcharacteristic of the semiconductor device of the sixth embodiment.

[0093]FIG. 32 is an equivalent circuit diagram showing a semiconductordevice according to a seventh embodiment of the present invention.

[0094]FIGS. 33A through 33D are cross-sectional views showing respectiveprocess steps for fabricating the semiconductor device of the seventhembodiment.

[0095]FIG. 34A is a diagram showing an equivalent circuit in a coarsecontrol in which stored information is changed largely in thesemiconductor device of the seventh embodiment. FIG. 34B is a graphshowing an equivalent circuit in a fine control in which storedinformation is changed slightly in the semiconductor device of theseventh embodiment.

[0096]FIG. 35 is a graph showing an applied voltage-pass currentcharacteristic of a ferroelectric capacitor used in the semiconductordevice of the seventh embodiment.

[0097]FIG. 36 is a graph showing an example of a method for applying avoltage in the semiconductor device of the seventh embodiment.

[0098]FIG. 37 is graph showing an applied voltage-drain currentcharacteristic of the semiconductor device of the seventh embodiment inan initial state.

[0099]FIG. 38 is a graph showing a drain current in the case where avoltage of +6 V is applied and then a pulse voltage is continuouslyapplied in the semiconductor device of the seventh embodiment.

[0100]FIG. 39 is a graph showing an applied voltage-drain currentcharacteristic of the semiconductor device of the seventh embodimentwhen scanned in the applied-voltage range of ±2 V after the applicationof a voltage of +6V.

[0101]FIG. 40 is a graph showing a drain current in the case where avoltage of −6 V is applied and then a pulse voltage is continuouslyapplied in the semiconductor device of the seventh embodiment.

[0102]FIG. 41 is a graph showing an applied voltage-drain currentcharacteristic of the semiconductor device of the seventh embodimentwhen scanned in the applied-voltage range of ±2 V after the input of apulse voltage of −6 V.

[0103]FIG. 42A is a circuit diagram showing a semiconductor deviceaccording to an eighth embodiment of the present invention. FIG. 42B isa graph showing a varistor characteristic of a resistor.

[0104]FIG. 43 is a cross-sectional view showing a structure of thesemiconductor device of the eighth embodiment.

[0105]FIG. 44 is a circuit diagram showing a semiconductor deviceaccording to a ninth embodiment of the present invention.

[0106]FIG. 45 is a circuit diagram showing a semiconductor deviceaccording to a tenth embodiment of the present invention.

[0107]FIG. 46 is a circuit diagram showing a semiconductor deviceaccording to an eleventh embodiment of the present invention.

[0108]FIG. 47 is a diagram schematically showing a fundamental structureof a neurocomputer according to a twelfth embodiment of the presentinvention.

[0109]FIG. 48 is a diagram showing a model representing a simplifiedstructure of a fundamental unit of the brain of an animal.

[0110]FIG. 49 is a cross-sectional view showing a known semiconductordevice functioning as a multilevel memory.

[0111]FIG. 50 is a graph showing hysteresis characteristics of the knownsemiconductor device functioning as a multilevel memory.

[0112]FIG. 51 is a graph showing the relationship between a gate voltageand a drain current in a memory cell of the known semiconductor device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0113] Embodiment 1

[0114] Hereinafter, a first embodiment of the present invention will bedescribed with reference to the drawings.

[0115]FIG. 1 is a top plan view of a multilevel memory according to thefirst embodiment of the present invention. FIG. 2 is a cross-sectionalview taken along the line II-II in FIG. 1. FIG. 3 is a cross-sectionalview taken along the line III-III in FIG. 1. In FIGS. 1, 2 and 3,identical components are denoted by respectively identical referencenumerals. In FIG. 1, only the components located on the uppermostsurface are indicated by solid lines. Some of reference numerals of theportions that are commonly shown in FIGS. 2 and 3 are omitted for betterviewability.

[0116] As shown in FIG. 2, the multilevel memory of this embodimentincludes: a p-type Si substrate 1; an isolation film 5 of silicon oxideformed by a LOCOS process in the Si substrate 1; a gate insulating film7 of silicon oxide having a thickness of 3 nm and formed on an activeregion of the Si substrate 1 defined by the isolation film 5; a gateelectrode 9 formed on the gate insulating film and made of polysiliconcontaining an n-type impurity; drain and source regions 3 a and 3 b thatare formed in the Si substrate 1 to the sides of the gate electrode 9,are in contact with the isolation film 5 and contain an n-type impurity;a plug interconnect 13 c connecting the drain region 3 a to a pad 15 a;a plug interconnect 13 d connecting the source region 3 b to a pad 15 b;a first interlevel dielectric film 11 filling in the gap between theplug interconnects 13 c and 13 d; a first ferroelectric layer 16 ofbismuth titanate (BIT) formed on the first interlevel dielectric film 11and having a thickness of 100 nm; a second ferroelectric layer 18 of BITformed on the first ferroelectric layer 16 and having a thickness of 400nm; a second interlevel dielectric film 21 of silicon oxide formed onthe second ferroelectric layer 18; an interconnect 25 c formed on thesecond interlevel dielectric film 21; an interconnect 25 a formedthrough the first and second ferroelectric layers 16 and 18 and thesecond interlevel dielectric film 21 to connect the pad 15 a to theinterconnect 25 c; and an interconnect 25 b connected to the pad 15 bthrough the first and second ferroelectric layers 16 and 18 and thesecond interlevel dielectric film 21. In this embodiment, the gatelength of the gate electrode 9 is 0.5 μm and the gate width thereof is 5μm.

[0117] As shown in FIG. 3, the multilevel memory of this embodimentincludes: the p-type Si substrate 1; the isolation film 5 made of asilicon oxide film formed by a LOCOS process in the Si substrate 1; thegate insulating film 7 of silicon oxide having a thickness of 3 nm andformed on the active region of the Si substrate 1 defined by theisolation film 5; the gate electrode 9 formed on the gate insulatingfilm 7 and made of polysilicon containing an n-type impurity; the firstinterlevel dielectric film 11 of silicon oxide formed on the gateelectrode 9 and the isolation film 5; a first intermediate electrode 14a of Pt/TiN formed on the first interlevel dielectric film 11 and havinga size of 0.5 μm×0.5 μm; a second intermediate electrode 14 b of Pt/TiNformed on the first interlevel dielectric film 11 and having a size of0.5 μm×0.5 μm; a plug interconnect 13 a formed through the firstinterlevel dielectric film 11 to connect the gate electrode 9 to thefirst intermediate electrode 14 a; a plug interconnect 13 b formedthrough the first interlevel dielectric film 11 to connect the gateelectrode 9 to the second intermediate electrode 14 b; the firstferroelectric layer 16 of BIT formed on the first interlevel dielectricfilm 11 and the first and second intermediate electrodes 14 a and 14 band having a thickness of 100 nm; a first upper electrode 17 of Pt/TINthat is formed on the first ferroelectric layer 16, is in parallel withthe first intermediate electrode 14 a to face the first intermediateelectrode 14 a, and has a size of 0.5 μm×0.5 μm; the secondferroelectric layer 18 of BIT formed on the first ferroelectric layer 16and having a thickness of 400 nm; a second upper electrode 19 of Pt/TiNthat is formed on the second ferroelectric layer 18, is in parallel withthe second intermediate electrode 14 b to face the second intermediateelectrode 14 b, and has a size of 0.5 μm×0.5 μm; the second interleveldielectric film 21 of silicon oxide formed on the second ferroelectriclayer 18; and the interconnect 25 c, which penetrates through the secondferroelectric layer 18 and the second interlevel dielectric film 21 toconnect with the first upper electrode 17 and penetrates through thesecond interlevel dielectric film 21 to connect with the second upperelectrode 19 by way of the upper face of the second interleveldielectric film 21.

[0118] A ferroelectric capacitor made up of a part of the firstferroelectric layer 16 and the first intermediate electrode 14 a and thefirst upper electrode 17, between which the first ferroelectric layer 16is sandwiched, is herein referred to as a capacitor MFM1. Aferroelectric capacitor made up of a part of the first and secondferroelectric layers 16 and 18, the second intermediate electrode 14 band the second upper electrode 19, between which the first and secondferroelectric layers 16 and 18 are sandwiched, is herein referred to asa capacitor MFM2. The capacitors MFM1 and MFM2 together form a capacitorMFMs.

[0119]FIG. 5 is an equivalent circuit diagram showing the multilevelmemory of this embodiment.

[0120] As shown in FIG. 5, the multilevel memory of this embodiment hasa structure in which the two ferroelectric capacitors are disposed inparallel and connected to each other above the gate electrode of the MOStransistor. In FIG. 5, the ferroelectric layer of the capacitor MFM1 hasa thickness of 100 nm and the electrode thereof has a size of 0.5 μm×0.5μm. The ferroelectric layers of the capacitor MFM2 have a thickness of500 nm and the electrode thereof has a size of 0.5 μm×0.5 μm.

[0121]FIGS. 4A through 4E are cross-sectional views showing respectiveprocess steps for fabricating the multilevel memory of this embodiment.The cross-sectional views in FIGS. 4A through 4E are taken along theline III-III in FIG. 1. Hereinafter, a method for fabricating themultilevel memory of this embodiment will be described with reference toFIGS. 4A through 4E.

[0122] First, in a process step shown in FIG. 4A, a p-type Si substrate1 is subjected to oxidation using silicon nitride (not shown) as a maskthrough a LOCOS process, thereby forming an isolation film 5.Thereafter, the silicon nitride (not shown) is dissolved by heatedphosphoric acid, for example. Then, the Si substrate 1 is thermallyoxidized at 900° C., for example, thereby forming a silicon oxide filmwith a thickness of 3 nm on the Si substrate 1. This silicon oxide filmis a gate insulating film 7. Then, polycrystalline silicon doped withphosphorus is deposited by a LPCVD process to form a gate electrode 9.Subsequently, the gate electrode 9 and the gate insulating film 7 arepatterned through dry etching. Boron ions are then implanted intoportions on the sides of the gate electrode 9 using the gate electrode 9as a mask, and then heat treatment is performed at 900° C. for 30minutes, thereby forming drain and source regions 3 a and 3 b shown inFIG. 2. The MOS transistor fabricated in this process step has a gatelength of 0.5 μm and a gate width of 5 μm.

[0123] Next, in a process step shown in FIG. 4B, silicon dioxide (SiO₂)is deposited over the substrate by an LPCVD process, thereby forming afirst interlevel dielectric film 11. Then, dry etching is performedusing a resist mask formed on the first interlevel dielectric film 11 sothat contact holes are formed, and thereafter, polysilicon is depositedby an LPCVD process in the contact holes. Subsequently, the polysiliconis planarized by a CMP process, thereby forming plug interconnects 13 a,13 b, 13 c and 13 d. Then, after titanium nitride has been deposited bya sputtering process to a thickness of 20 nm over the first interleveldielectric film 11, a Pt layer is deposited by a sputtering process to athickness of 50 nm. Subsequently, silicon oxide that has been depositedby a sputtering process over the Pt layer is patterned to form a hardmask (not shown). The Pt/TiN layer is patterned by Ar milling using thehard mask as a mask, thereby forming first and second intermediateelectrodes 14 a and 14 b and pads 15 a and 15 b shown in FIG. 2.Thereafter, the hard mask made of silicon oxide, for example, is removedby diluted hydrofluoric acid or the like.

[0124] Then, in a process step shown in FIG. 4C, BIT is deposited by asputtering process to a thickness of 100 nm over the substrate underconditions that the substrate temperature is 550° C., the partialpressure of oxygen is 20% and the RF power is 100W, thereby forming afirst ferroelectric layer 16. Then, a Pt layer is deposited by asputtering process and then is patterned by Ar milling using a hard maskof silicon oxide (not shown), thereby forming a first upper electrode17. Thereafter, the hard mask of silicon oxide (not shown) is removed bydiluted hydrofluoric acid or the like. In this embodiment, each of thefirst intermediate electrode 14 a and the first upper electrode 17 has asize of 0.5 μm×0.5 μm.

[0125] Then, in a process step shown in FIG. 4D, BIT is deposited by asputtering process to a thickness of 400 nm over the substrate underconditions that the substrate temperature is 550° C., the partialpressure of oxygen is 20% and the RF power is 100W, thereby forming asecond ferroelectric layer 18. Then, a Pt layer is deposited by asputtering process over the second ferroelectric layer 18 and then ispatterned by Ar milling using a hard mask of silicon oxide (not shown),thereby forming a second upper electrode 19. Thereafter, the hard mask(not shown) is removed by diluted hydrofluoric acid or the like. In thisembodiment, each of the second intermediate electrode 14 b and thesecond upper electrode 19 has a size of 0.5 μm×0.5 μm.

[0126] Then, in a process step shown in FIG. 4E, a silicon oxide film isdeposited over the substrate by plasma CVD using TEOS, and then isplanarized by a CMP process, thereby forming a second interleveldielectric film 21. Thereafter, the second interlevel dielectric film 21is dry-etched using a resist mask formed on the second interleveldielectric film so that a contact hole reaching the second upperelectrode 19 is formed. On the other hand, the second interleveldielectric film 21 and the second ferroelectric layer 18 are dry-etchedusing a resist mask formed on the second interlevel dielectric film sothat a contact hole reaching the first upper electrode 17 is formed. Ifthe etching selectivity of the second ferroelectric layer 18 to theupper electrode 19 is sufficiently high, the contact hole reaching thesecond upper electrode 19 and the contact hole reaching the first upperelectrode 17 can be formed simultaneously. Then, an AlSiCu alloy isdeposited by a sputtering process in the contact holes and then isdry-etched, thereby forming interconnects 25 a, 25 b and 25 c,respectively.

[0127] In this manner, the multilevel memory of this embodiment isfabricated.

[0128]FIG. 6 is a graph showing a polarization-voltage hysteresischaracteristic (P-V characteristic) of the capacitor MFM1. FIG. 6 showsa hysteresis characteristic when only the capacitor MFM1 is connected toa power source.

[0129] Referring to FIG. 6, it is found that since the thickness of thecapacitor MFM1 is as small as about 100 nm, the coercive voltage thereofis low, while the polarization value at a voltage of 0 V after theapplication of a voltage of about 5V or higher (i.e., remanentpolarization) is about 4 μC/cm², reflecting properties of the BITmaterial.

[0130]FIG. 7 is a graph showing a P-V characteristic of the capacitorMFM2. Though the capacitor MFM2 is made of the same ferroelectricmaterial, i.e., BIT, as that of the capacitor MFM1, the thickness of thecapacitor MFM2 is as thick as 500 nm in total. Therefore, the coercivevoltage thereof is about five times higher than that of the capacitorMFM1 as shown in FIG. 7. However, since remanent polarization values aredetermined by the material, the remanent polarization value of thecapacitor MFM2 is about 4 μC/cm², which is substantially equal to thatof the capacitor MFM1.

[0131] A method for driving the multilevel memory of this embodimentwith the structure in which two ferroelectric capacitors having mutuallydifferent hysteresis characteristics are connected in parallel asdescribed above, and operation of the multilevel memory will bedescribed with reference to FIGS. 8 through 10.

[0132]FIG. 10 is a graph showing a voltage applied between the uppergate electrode and the lower electrode and the effective polarizationsof the two ferroelectric capacitors in the multilevel memory of thisembodiment. As shown in FIG. 10, since the capacitors used in themultilevel memory of this embodiment are connected to each other inparallel, the polarization of the whole of the capacitors has an averagevalue corresponding exactly to the ratio between areas for thepolarizations of the capacitors MFM1 and MFM2.

[0133]FIG. 8 is a graph for describing hysteresis characteristics ofpolarization in the whole of the capacitors (i.e., the capacitor MFMs)made up of the capacitors MFM1 and MFM2 connected in parallel. In FIG.8, the average value of the polarizations of the two capacitorsindicated by broken lines determines the polarization of the capacitorMFMs. That is to say, the polarization of the capacitor MFMs exhibitsthe hysteresis characteristics shown in FIG. 10.

[0134] In a range x shown in FIG. 8, the polarization of the capacitorMFM2 hardly varies with the change in the voltage V. On the other hand,the polarization of the capacitor MFM1 increases abruptly in the firsthalf of the range x and varies slightly in the latter half, with thechange in the voltage V. As a result, the synthesized value of thesepolarizations changes abruptly in the first half of the range x andvaries gently in the latter half of the range x. On the other hand, in arange y, the polarization of the capacitor MFM2 changes abruptly withthe change in the voltage V, while the polarization of the capacitorMFM1 hardly varies with the change in the voltage V. As a result, thesynthesized value of these polarizations changes abruptly in the firsthalf of the range y but more gently than the polarization value of thecapacitor MFM2 alone.

[0135] The multilevel memory of this embodiment includes the twoferroelectric capacitors having mutually different coercive voltages asdescribed above. Thus, unlike the general hysteresis loops as shown inFIG. 6, the hysteresis loop of the multilevel memory of this embodimenthas a metastable point as indicated by a point C in FIG. 10. Therefore,the polarization changes gently with the change in voltage in thevicinity of 4 V of a write voltage. As a result, even if the writevoltage is swung by noise, for example, the change in polarization canbe suppressed.

[0136] To achieve this effect, ranges in which hysteresis loops exhibitabrupt changes in polarizations with the change in voltage should notcoincide with each other. Thus, the coercive voltages of the capacitorsare required to differ from each other. In particular, in the first halfstage of the range in which the polarization are from zero tosaturation, if two dielectric materials exhibiting mutually differentrates of changes in polarizations with the change in voltage are used, ametastable point can be created as intended. In the same manner, in thecase where three or more capacitors are arranged in parallel, thedifference between the coercive voltages of the capacitors is alsorequired to differ sufficiently.

[0137]FIG. 9 is a graph showing a P-V characteristic of capacitors inthe case where a capacitor MFM3 having the same area as that of thecapacitor MFM1 or MFM2 is added to the capacitors MFM1 and MFM2. The P-Vcharacteristic of the whole of the capacitors is indicated by brokenlines in FIG. 9. As in the case where two capacitors are provided, thecoercive voltages of the capacitors are mutually different from eachother. Thus, a metastable point F is additionally created on thehysteresis loop. In this case, the point C shifts to the point C′. Inthis manner, information can be stored with stability using at leastfour levels.

[0138] Next, a method for conducting a multilevel operation of theferroelectric capacitors arranged in parallel in this embodiment will bedescribed.

[0139] First, in FIG. 10, the line connecting points A, S, C, D and Pindicates the polarization of the capacitors upon the application ofrespective voltages. When the applied voltage is increased from −8 V,the polarization of the capacitors shifts from the point A to the pointS and then to the point C along the direction shown by the allows. Whena voltage of 8 V is applied, the polarization of the capacitors issaturated and does not increase, so that the polarization state remainsat the point D even upon the application of higher voltages. When thevoltage applied to the capacitors is once increased to 8 V and then isdecreased, the polarization state of the capacitors approaches the pointA by way of the point P. When the applied voltage is −8 V, thepolarization state returns to the point A.

[0140] Hereinafter, respective states of the capacitors MFM1 and MFM2will be described. At the point A at which a voltage of −8 V is appliedto the capacitors, the polarizations of the capacitors MFM1 and MFM2 aresaturated, being negatively charged, as shown in FIGS. 6 and 7. In thisstate, when the voltage applied to the capacitors is removed, theapplied voltage becomes 0 V so that the polarizations state is at thepoint S. Since the capacitors MFM1 and MFM2 have the same size, thepolarization of the capacitor MFMs takes the average value of thecapacitors MFM1 and MFM2 shown in FIGS. 6 and 7 (see FIG. 8).

[0141] Next, when the applied voltage at the point S is increased toabout 4V, the polarization of the capacitor MFM1 is saturated, beingpositively charged, while the polarization of the capacitor MFM2 ispositively charged but is not saturated. The polarizations of the twocapacitors are averaged at the point C, which is a metastate point. FIG.10 shows that a voltage of 3.5 V is applied to the capacitors inconsideration of a noise margin, so that the polarization state is atthe point B. Then, the applied voltage is removed, so that the stateindicated by the point Q at which the polarization is substantially 0μC/cm² is created.

[0142] Then, when the voltage applied to the capacitors is increased to8 V, the polarization state of the capacitors is at the point D at whichpolarizations of the capacitors MFM1 and MFM2 are both saturated with apositive charge. Thereafter, the voltage is removed, so that thepolarization state of the capacitors is at the point P.

[0143] Then, the voltage applied to the capacitors is decreased to −8 V,so that the polarization state of the capacitors returns to the point A.

[0144] In this manner, by applying three levels of write voltages suchas −8 V, 3.5 V and 8V, the multilevel memory of this embodiment canperform a stable storing operation toward noise, for example.

[0145]FIG. 11 is a graph showing a drain current in the case where agate voltage, which is a read voltage, is changed after write operationsat voltages of +8 V, +3.5 V and −8 V, respectively, have been performedin the multilevel memory of this embodiment.

[0146] As shown in FIG. 11, in the read voltage range of 2 V to 3 V,values of a current flowing into drain in the respective polarizationstates may differ by one or more orders of magnitude, and storedinformation can be read out with stability.

[0147] Next, a write operation at a point on a hysteresis loop at whichthe write operation is likely to be unstable will be described, with thecase where a write voltage of half of the saturation voltage swings 10%taken as an example.

[0148]FIG. 12 is a graph for describing how much the polarization valueshifts when a write voltage swings 10% in the known multilevel memoryprovided with a single ferroelectric capacitor.

[0149]FIG. 13 is a graph showing a portion A in FIG. 12 undermagnification.

[0150] As can be understood from FIGS. 12 and 13, the known techniquehas no other choice but to use a portion in the hysteresis loop wherethe polarization changes abruptly in order to obtain a polarizationstate at a point on the hysteresis loop, and therefore the polarizationvalue shifts greatly between 1.4 μC/cm² and 2.0 μC/cm², which isoriginally expected to be 1.7 μC/cm², with respect to the shifts of 10%(see FIG. 13).

[0151]FIG. 14 is a graph for describing shifts in the polarization whena write voltage swings in the multilevel memory of this embodiment, asin FIGS. 12 and 13. FIG. 15 shows a portion B in FIG. 14 undermagnification.

[0152] As can be understood from FIGS. 14 and 15, abrupt change inpolarization with the swings in the write voltage is greatly improved inthe multilevel memory of this embodiment as compared to the knowntechnique. For example, the polarization value shifts in the range of−0.1 μC/cm² to −0.2 μC/cm², both inclusive, which is originally expectedto be −0.15 μC/cm², with respect to voltage swings of ±10%. That is tosay, the range of the shift in polarization value is considerablyimproved to be 0.1 μC/cm² or less, as compared to the known technique inwhich the range of the shift in polarization value is 0.6 μC/cm². Thisis because the ferroelectric capacitors are connected in parallel andthe respective coercive voltages are made different from one another,resulting in creating a metastable point on the hysteresis loop.

[0153] Swings in a write voltage (electric field strength in writing)may be caused by variations such as variation in thickness of aferroelectric layer and variation in dielectric constant due to thedifference in crystallinity of the ferroelectric layer as well as noise.The write voltage swings of ±10% possibly occur in practicalapplication.

[0154] Accordingly, the structure of the multilevel memory of thisembodiment can enlarge a margin in a process by suppressing the shift inpolarization value, and therefore is useful for actual devicefabrication.

[0155]FIGS. 16 and 17 are graphs showing effective polarization valueswhen the ratio between the areas of the capacitors MFM1 and MFM2 ischanged in the case where the ferroelectric film of the capacitor MFM1has a thickness of 100 nm and the ferroelectric film of the capacitorMFM2 has a thickness of 1000 nm. At points D, A, B and E in FIGS. 16Athrough 16D and FIGS. 17A through 17D, voltages are applied such that apositive-side maximum polarization, a negative-side maximumpolarization, a positive-side intermediate polarization and anegative-side intermediate polarization are written, respectively. Thepolarization values after the removal of these voltages are indicated bypoints P, S, Q and R, respectively.

[0156]FIGS. 16A through 16D are graphs showing effective polarizationsin the case where the area of the capacitor MFM2 is increased graduallywith respect to the area of the capacitor MFM1. As shown in FIGS. 16Athrough 16D, as the area ratio of the capacitor MFM2 increases, thepolarization changes abruptly with the voltage change in the rangeswhere the hysteresis loop passes through the points B and E.

[0157] On the other hand, FIGS. 17A through 17D are graphs showingeffective polarizations in the case where the area ratio of thecapacitor MFM1 is increased. As shown in FIGS. 17A through 17D, thepolarization varies gently with the voltage change in the ranges wherethe hysteresis loop passes through the points B and E. This fact showsthat, as for the area ratio between the capacitors MFM1 and MFM2, if thearea of the capacitor MFM1 is larger than that of the capacitor MFM2, amultilevel memory which is more stable to swings in a write voltage canbe implemented. However, as can be seen from FIG. 17D, if the area ratioof the capacitor MFM1 is extremely high, the points P and Q approacheach other and the points S and R approach each other, resulting in thatit is difficult to determine data. Accordingly, in this embodiment, evenif the area ratio between the capacitors MFM1 and MFM2 (the area of thecapacitor MFM1/the area of the capacitor MFM2) is set substantially inthe range of 0.5 to 2, separation of stored information is maintainedexcellent, and a stable multilevel operation is achieved.

[0158] If the effective polarization value is not at the points Q and R,but is 0 μC/cm², i.e., if three states of polarizations are used,separation of stored information is maintained excellent even with thearea ratio between the capacitors MFM1 and MFM2 (the area of thecapacitor MFM1/the area of the capacitor MFM2) substantially in therange of 0.2 to 2.

[0159] As has been described above, according to this embodiment, if twoor more ferroelectric capacitors having the same polarization directionand having mutually different coercive voltages are connected to thegate electrode of a field-effect transistor, it is possible to achieve amultilevel memory in which a drain current varies only slightly with thesmall variation in a write voltage.

[0160] According to this embodiment, a stable highly-integratedsemiconductor memory can be provided. In addition, the memory isexpected to be applied, as a nonvolatile transistor having a pluralityof resistance values, to neuron elements mimicking neurons of the brain.

[0161]FIG. 18 is a cross-sectional view showing a modified example ofthe multilevel memory of this embodiment. This multilevel memory has thesame structure as that of the multilevel memory of this embodiment shownin FIG. 3 except for the second ferroelectric layer 18, and thus thedescription of the structure is herein omitted.

[0162] The multilevel memory of this modified example includes aparaelectric instead of the second ferroelectric layer 18 used in themultilevel memory of this embodiment shown in FIG. 3.

[0163] For example, in this modified example of this embodiment,tantalum oxide having a thickness of 100 nm and formed by a sputteringprocess is used as a paraelectric layer 20. The tantalum oxide layer hasa relative dielectric constant of about 25 in this modified example ofthis embodiment. In this case, the paraelectric layer has a capacitanceof about one-fourth of that of the ferroelectric layer, so thatone-fifth of the voltage applied to the capacitor MFM2 is applied to theferroelectric. Therefore, the apparent coercive voltage increasesfivefold, and thus a metastable point can be created before thepolarization of the whole of the capacitors is saturated.

[0164] In this embodiment, in obtaining the ferroelectric capacitorshaving mutually difference coercive voltages, the thicknesses of theferroelectric layers are 100 nm and 500 nm, respectively, or 100 nm and1000 nm, respectively. Alternatively, the thicknesses may take arbitraryvalues as well as the values described above. In such a case, thecoercive voltages of the capacitors can be made differ from each other.

[0165] Alternatively, ferroelectrics made of different materials may berespectively applied to the ferroelectric capacitors. Then, the sameeffect is obtained as in the case where the thicknesses of theferroelectric layers are made different from each other. For example,BIT used in this embodiment has a coercive force of about 20 kV/cm andPZT has a different coercive force, i.e., about 40 kV/cm. Thus, thecoercive voltage of the capacitor using PZT is twice as large as that ofthe capacitor using BIT so long as the ferroelectric layers of thecapacitors have the same thickness.

[0166] The multilevel memory of this embodiment has been describedparticularly in the case where two ferroelectric capacitors areprovided. Alternatively, three or more ferroelectric capacitors havingdifferent coercive voltages may be connected as shown in FIG. 9. In sucha case, the number of metastable points created on the hysteresysincreases in the same manner, so that a ferroelectric gate memory withmore levels can be implemented.

[0167] In the multilevel memory of this embodiment, the positive andnegative states of the polarizations of the capacitors MFM1 and MFM2coincide with each other. Alternatively, these capacitors may bepolarized in opposite orientations.

[0168] Embodiment 2

[0169]FIG. 19 is a cross-sectional view showing a structure of amultilevel memory according to a second embodiment of the presentinvention. As shown in FIG. 19, the multilevel memory of this embodimentincludes: a p-type substrate 1; an isolation film (not shown) of siliconoxide formed in the Si substrate 1; a gate insulating film 7 of siliconoxide formed on the Si substrate 1; gate and lower electrodes 26 ofPt/TiN formed on the gate insulating film 7; a first ferroelectric layer27 of BIT formed on the gate and lower electrodes 26 and having athickness of 100 nm; a first upper electrode 29 which is formed on thefirst ferroelectric layer 27 and is not longer than half of the gateelectrode in width; a second ferroelectric layer 28 of BIT which isformed on the first ferroelectric layer 27, is not longer than half ofthe gate electrode in width and has a thickness of 400 nm; a secondupper electrode 30 formed on the second ferroelectric layer 28; aninterlevel dielectric film 31 formed on the gate insulating film 7 andfilling in the gap located on the sides of the gate and lower electrodes26, first ferroelectric layer 27, first upper electrode 29, secondferroelectric layer 28, and first and second upper electrodes 29 and 30;and a plug interconnect 32 formed through the interlevel dielectric filmto connect with the first and second upper electrodes 29 and 30. In thisembodiment, the gate and lower electrodes 26 are formed by merging agate electrode with a lower electrode of a capacitor.

[0170] In this embodiment, a capacitor MFM1 made up of the first upperelectrode 29, the first ferroelectric layer 27 and the lower electrode26 and a capacitor MFM2 made up of the second upper electrode 30, thesecond ferroelectric layer 28, the first ferroelectric layer 26 and thelower electrode 26 have mutually different coercive voltages. Thus, ametastable point is created on a hysteresis loop of the whole of thecapacitors. Therefore, the multilevel memory of this embodiment achievesa stable multilevel operation exhibiting excellent separation of storedinformation, as the multilevel memory of the first embodiment.

[0171] In the multilevel memory of this embodiment, no intermediateelectrode is needed. Therefore, the number of fabrication process stepscan be reduced as compared to the multilevel memory of the firstembodiment, thus reducing the fabrication cost.

[0172] A paraelectric layer may be used instead of the secondferroelectric layer 28 used in this embodiment. In such a case, thecapacitors MFM1 and MFM2 also have mutually different coercive voltages.

[0173] Embodiment 3

[0174]FIG. 20 is a circuit diagram showing a multilevel memory accordingto a third embodiment of the present invention. As shown in FIG. 20, themultilevel memory of this embodiment includes: a selecting transistorTr1 whose gate is connected to a word line WL and whose drain isconnected to a bit line BL; and capacitors MFM1 and MFM2 arranged inparallel and connected to source of the selecting transistor Tr and eachincluding a ferroelectric. In the multilevel memory of this embodiment,the capacitors MFM1 and MFM2 have mutually different coercive voltages.

[0175] The multilevel memory of this embodiment is a memory called anFeRAM that reads out information depending on the amount of currentflowing when the polarization of the capacitors is inverted. In thiscase, in the multilevel memory of this embodiment, a plurality ofremanent polarization values can be obtained with stability byconnecting the capacitors having mutually different coercive voltages inparallel, as described in the first and second embodiments. In the readoperation of the multilevel memory of this embodiment, while a givenvoltage, e.g., 8V, is kept on the word line WL, the amount of currentthat has flowed through the selecting transistor Tr1 is determineddepending on the degree of a voltage drop at the word line WL causedwhen the selecting transistor Tr1 is turned ON (conductive), therebyreading out information. In this case, the amount of polarizationinversion varies depending on the state of the remanent polarization ofthe ferroelectric capacitors, so that the amount of current flowingthrough the transistor Tr1 varies. For example, a larger amount ofcurrent (an absolute value) is detected in the order of the points P, Qand S in FIG. 10. That is to say, a multilevel FeRAM is implementable.

[0176] This structure also achieves a stable multilevel operation withexcellent separation of stored information, as in the multilevel memoryof the first embodiment.

[0177] Embodiment 4

[0178]FIG. 21 is an equivalent circuit diagram showing a multilevelmemory according a fourth embodiment of the present invention. Themultilevel memory of this embodiment has a structure in which acapacitor 40 is interposed between the gate electrode 9 of themultilevel memory and the capacitor MFM2 of the first embodiment.Specifically, the multilevel memory of this embodiment includes: an MIStransistor; capacitors MFM1 and MFM2 arranged in parallel, connected tothe gate electrode 9 of the MIS transistor and each including aferroelectric; and the capacitor 40 interposed between the gateelectrode 9 and the capacitor MFM2. In FIG. 21, components also shown inFIG. 5 are identified by the same reference numerals. The areas of thecapacitors MFM1 and MFM2 and the thicknesses of the ferroelectric layersare the same as those in the first embodiment. The capacitor 40 is acapacitor including a paraelectric but may be a ferroelectric capacitor.

[0179] When a voltage is applied to the multilevel memory of the firstembodiment, voltages applied to the capacitors MFM1 and MFM2 are equalto each other. On the other hand, in the multilevel memory of thisembodiment, the sum of the voltages distributed to the capacitor MFM2and the capacitor 40 is equal to the voltage distributed to thecapacitor MFM1.

[0180] Therefore, in this embodiment, the voltage distributed to thecapacitor MFM2 is smaller than the voltage distributed to the capacitorMFM2 in the first embodiment, upon the application of the same voltageto the multilevel memories. As a result, an apparent coercive voltage ishigher than that in the first embodiment. In the multilevel memory ofthis embodiment, the capacitors MFM1 and MFM2 have mutually differentcoercive voltages, and a metastable point is created on the hysteresisloop of these capacitors. Accordingly, multilevel information can bestored in the multilevel memory of this embodiment with stability.

[0181] In addition, interposing at least one capacitor between aferroelectric capacitor and the gate electrode of an MIS transistorallows an apparent coercive voltage to be adjusted to an arbitraryvalue, so that flexibility in design improves. In this embodiment, thecapacitors MFM1 and MFM2 have mutually different coercive voltages.However, even if the coercive voltages of the two capacitors are equalto each other, a multilevel memory in which multilevel information isstored with stability is implementable because an apparent coercivevoltage of the capacitor MFM2 is varied by interposing the capacitor 40.The multilevel memory of this embodiment is advantageous in that theferroelectric layers of the capacitors MFM1 and MFM2 can be formed at atime.

[0182] In this embodiment, one capacitor is interposed between thecapacitor MFM2 and the gate electrode 9 of the MIS transistor.Alternatively, two or more capacitors may be interposed therebetween.

[0183] Embodiment 5

[0184] Hereinafter, a semiconductor device according to a fifthembodiment of the present invention will be described with reference tothe drawings.

[0185]FIG. 22 is an equivalent circuit diagram showing the semiconductordevice of this embodiment. As shown in FIG. 22, the semiconductor deviceof this embodiment is characterized by including: a control-voltagesupply unit 110; a field-effect transistor (which will be hereinafterreferred to as an MOS transistor); a dielectric capacitor 104; and aresistor 106. The dielectric capacitor 104 and the resistor 106 aredisposed in parallel and interposed between a gate electrode 109 of theMOS transistor and the control-voltage supply unit 110.

[0186]FIG. 23 shows a top plan view of the semiconductor device of thisembodiment. FIG. 24 shows a cross-sectional view taken along the lineXXIV-XXIV in FIG. 23. FIG. 25 shows a cross-sectional view taken alongthe line XXV-XXV in FIG. 23. In FIG. 23, hatch patterns are omitted andonly components on the uppermost surface are indicated by solid linesfor better viewability. Some of the components also shown in FIGS. 24and 25 are also omitted for better viewability. In FIGS. 24 and 25,components behind the cross section are omitted in part.

[0187] As shown in FIGS. 23, 24 and 25, the semiconductor device of thisembodiment includes: a p-type Si substrate 101 including an activeregion, for example; a substrate electrode 108 (shown only in FIG. 22)formed on a plane facing the active region of the Si substrate 101; anisolation oxide film 105 formed in the Si substrate 101 to surround theactive region; a gate insulating film 107 of SiO₂ having a thickness of5 nm and formed on the Si substrate 101; a gate electrode 109 formed onthe gate insulating film 107 and made of polysilicon containingphosphorus; drain and source regions 103 a and 103 b formed in the Sisubstrate 101 to the sides of the gate electrode 109 and containing ann-type impurity; a first interlevel dielectric film 111 formed on the Sisubstrate 101 and made of an insulator such as SiO₂; pads 115 a and 115b and an intermediate electrode 114 that are formed on the firstinterlevel dielectric film 111 and made of a titanium nitride (TiN) filmhaving a thickness of 20 nm and a Pt film having a thickness of 50 nm; aplug interconnect 113 a of polysilicon connecting the gate electrode 109to the intermediate electrode 114 through the first interleveldielectric film 111; plug interconnects 113 b and 113 c of polysiliconconnecting the drain region 103 a to the pad 115 a and connecting thesource region 103 b to the pad 115 b, respectively, through the firstinterlevel dielectric film 111; a dielectric layer 116 of bariumstrontium titanate (hereinafter referred to as BST) formed on the firstinterlevel dielectric film 111 and having a thickness of 100 nm; anupper electrode 119 of Pt formed on the dielectric layer 116 and havinga thickness of 50 nm; a second interlevel dielectric film 121 formed onthe dielectric layer 116; an interconnect 125 a made of a conductor suchas an AlSiCu alloy and penetrating through the second interleveldielectric film 121 to connect with the upper electrode 119; andinterconnects 125 b and 125 c made of a conductor such as an AlSiCualloy and penetrating through the second interlevel dielectric film 121and the dielectric layer 116 to connect with the pads 115 a and 115 b,respectively.

[0188] Each of the intermediate electrode 114 and the upper electrode119 has a size of 2.5 μm×4 μm, which is the same as the size of the MOStransistor including the gate electrode 109.

[0189] In the semiconductor device of this embodiment, the dielectriclayer 116 and the intermediate and upper electrodes 114 and 119, betweenwhich the dielectric layer 116 is sandwiched, together form a capacitor.In addition, the dielectric layer 116 also constitutes the resistor 106(see FIG. 22). Operation of the semiconductor device in consideration ofthis structure will be described later.

[0190] Next, a method for fabricating the semiconductor device of thisembodiment will be hereinafter described with reference to FIGS. 26Athrough 26D.

[0191]FIGS. 26A through 26D are cross-sectional views taken along theline XXV-XXV in FIG. 23 and showing respective process steps forfabricating the semiconductor device of this embodiment. Components notappeared in the XXV-XXV cross-sections in FIGS. 26A through 26D andcomponents omitted therein will be described using the referencenumerals used in the descriptions for FIGS. 23 through 25.

[0192] First, in a process step shown in FIG. 26A, a p-type Si substrate101 is subjected to oxidation using a silicon nitride film (not shown)formed thereon as a mask, thereby forming an isolation oxide film 105 (aLOCOS process). Thereafter, the silicon nitride film is removed byheated phosphoric acid, for example, and then the substrate is subjectedto a pyrogenic oxidation at 900° C., thereby forming a SiO₂ film with athickness of 5 nm on the Si substrate 101. Then, polysilicon doped withan n-type impurity such as phosphorus is deposited by a LPCVD process,for example, over the SiO₂ film and then is patterned by dry etching,thereby forming a gate insulating film 107 and a gate electrode 109.Subsequently, a p-type impurity such as boron is implanted using thegate electrode 109 as a mask, and then heat treatment is performed at900° C. for 30 minutes, thereby forming drain and source regions 103 aand 103 b in the Si substrate 101 to the sides of the gate electrode109. The MOS transistor fabricated in this process step has a gatelength of 1 μm and a gate width of 10 μm.

[0193] Next, in a process step shown in FIG. 26B, SiO₂ is deposited byan LPCVD process, for example, over the substrate, thereby forming afirst interlevel dielectric film 111. Then, after a resist pattern (notshown) has been formed on the first interlevel dielectric film 111, thefirst interlevel dielectric film 111 is dry-etched, thereby formingcontact holes reaching the gate electrode 109 and the drain and sourceregions 103 a and 103 b, respectively. Thereafter, polysilicon isdeposited by an LPCVD process, for example, over the substrate, and thenthe substrate surface is planarized by a CMP process, thereby formingplug interconnects 113 a, 113 b and 113 c filling in the respectivecontact holes. Then, after TiN has been deposited by a sputteringprocess to a thickness of 20 nm over the first interlevel dielectricfilm 111, Pt is deposited by a sputtering process to a thickness of 50nm. Subsequently, a SiO₂ film that has been deposited by a sputteringprocess is patterned to form a hard mask (not shown). The Pt/TiN layeris then patterned by Ar milling using the hard mask, thereby forming anintermediate electrode 114 and pads 115 a and 115 b on the pluginterconnects 113 a, 113 b and 113 c, respectively. Thereafter, the hardmask is removed by diluted hydrofluoric acid or the like.

[0194] In this case, the TiN layer is formed so as to prevent Pt andpolycrystalline silicon from forming silicide which increases theresistance.

[0195] Then, in a process step shown in FIG. 26C, BST is deposited by asputtering process, for example, over the first interlevel dielectricfilm 111 under conditions that the substrate temperature is 550° C., thepartial pressure of oxygen is 20% and the RF power is 100W, therebyforming a dielectric layer 116 with a thickness of 100 nm. Then, Pt isdeposited by a sputtering process on the dielectric layer 116 and thenis patterned by Ar milling using a hard mask of SiO₂ (not shown),thereby forming an upper electrode 119 facing the intermediate electrode114 with the dielectric layer 116 interposed therebetween. Thereafter,the hard mask is removed by diluted hydrofluoric acid or the like.

[0196] In this embodiment, each of the intermediate electrode 114 andthe upper electrode 119 has a size of 2.5 μm×4 μm, which is the same asthe size of the MOS transistor.

[0197] Then, in a process step shown in FIG. 26D, SiO₂ is deposited byplasma CVD using TEOS (tetraethylorthosilicate) and then is planarizedby a CMP process, thereby forming a second interlevel dielectric film121. Then, the second interlevel dielectric film 121 and the dielectriclayer 116 are dry-etched using a resist mask, thereby forming contactholes. Subsequently, an AlSiCu alloy is deposited by a sputteringprocess over the substrate and then is dry-etched using a resist mask,thereby forming interconnects 125 a, 125 b and 125 c on the secondinterlevel dielectric film 121 to connect with the upper electrode 119,the pad 115 a, and the pad 115 b, respectively. The interconnect 125 ais connected to a control-voltage supply unit 110 (not shown).

[0198] In this manner, the semiconductor device shown in FIG. 22 isfabricated.

[0199] The semiconductor device of this embodiment has a structure shownin the equivalent circuit in FIG. 22. However, in reality, as shown inFIGS. 23 through 26, the dielectric capacitor 104 having a structure inwhich the dielectric layer 116 is interposed between the intermediateelectrode 114 and the upper electrode 119 operates also as an electricresistor shown in FIG. 22. That is to say, the dielectric capacitor 104and the resistor 106 shown in FIG. 22 are one and the same, and electricresistance is a resistance component of the dielectric capacitor.Therefore, in the semiconductor device of this embodiment, the structureshown in the equivalent circuit in FIG. 22 is made simple, as comparedto the case where the dielectric capacitor 104 and the resistor 106 aredisposed separately.

[0200] Hereinafter, a driving method for and operation of thesemiconductor device of this embodiment will be described.

[0201]FIG. 27 is a graph showing a characteristic of a pass currentflowing between the intermediate electrode 114 and the upper electrode119 through the dielectric layer 116 upon the application of a voltageto both electrodes of the dielectric capacitor 104 including thedielectric layer 116 of BST. As shown in FIG. 27, the material BST has acharacteristic that the resistance value is almost constant while theelectric field intensity is low, so that a pass current value varies inproportion to the voltage. In FIG. 27, since the abscissa uses a logscale, the characteristic in the graph is represented by axisymmetriccurves with respect to 0V in the negative- and positive-voltage ranges.

[0202] A method for driving the semiconductor device of this embodimentincluding the dielectric layer 116 having such a characteristic andoperation of the device will be hereinafter described.

[0203]FIG. 28 is a graph showing a drain current-applied voltagecharacteristic for describing a driving method for and operation of thesemiconductor device of this embodiment. In FIG. 28, the abscissarepresents a voltage applied between the Si substrate 101 and theinterconnect 125 a (hereinafter simply referred to as an appliedvoltage), while the ordinate represents a drain current flowing betweenthe drain and source regions 103 a and 103 b. In evaluating the draincurrent-applied voltage characteristic for each of the semiconductordevices according to this embodiment and the following embodiments, avoltage of 1V is applied between the drain and source regions 103 a and103 b.

[0204] The semiconductor device of this embodiment has a structure inwhich the MOS capacitor, in which the gate insulating film 107 issandwiched between the Si substrate 101 and the gate electrode 109, andthe dielectric capacitor 104, in which the dielectric layer 116 issandwiched between the intermediate electrode 114 and the upperelectrode 119, are connected in series. Thus, in the semiconductordevice, the applied voltage is applied, being distributed to therespective capacitors.

[0205] For example, in an measurement of the semiconductor device ofthis embodiment shown in FIG. 28 where the applied voltage is set in therange of −3 V to +3 V, when the maximum voltage of +3 V is applied,voltages of 2.2 V and 0.8 V are respectively distributed to the MOScapacitor and the dielectric capacitor. As shown in FIG. 27, in thedielectric capacitor, a leakage current is very small in the voltagerange of −0.8 V to 0.8 V, both inclusive, in this measurement.

[0206] As shown in FIG. 28, when the semiconductor device of thisembodiment in an initial state operates at high speed and at a pulsevoltage with a frequency of about 1 MHz, for example, the semiconductordevice exhibits a characteristic represented by a characteristic curveincluding points A and O (hereinafter referred to as an A-O curve).

[0207] In the range not higher than about 0 V, though the A-O curve isnot shown therein, the drain current is at a noise level, i.e., at alevel sufficiently smaller than 10⁻⁸ (A). Therefore, when the appliedvoltage is 3 V, for example, a drain current of about 1×10⁻³ (A) flows(the point A in FIG. 28). When the applied voltage is then decreased to0 V, the drain current is at a noise level (the point O in FIG. 28).That is to say, when the semiconductor device of this embodimentoperates at a high speed of about 1 MHz, the drain current increasesaccording to the applied voltage, so that the device operates as the MOStransistor.

[0208] Next, if the state represented by the point A in FIG. 28, i.e.,the state in which a voltage of +3 V is applied to the upper electrode119, is maintained, a charge is gradually accumulated in theintermediate electrode 114 by the pass current flowing through thedielectric layer 116. In this state, a charge is also accumulated in thegate electrode 109 of the MOS transistor connected to the intermediateelectrode, thus changing the threshold value of the MOS transistor.Accordingly, the applied voltage-drain current characteristic of thesemiconductor device also changes.

[0209] For example, if an applied voltage of +3 V is held for 100seconds and then a voltage is applied to the upper electrode 119 atabout 1 MHz, the characteristic changes, drawing a curve includingpoints B and C in FIG. 28. That is to say, the applied voltage-draincurrent characteristic (hereinafter referred to as a VG-IDcharacteristic) of the MOS transistor can be changed using the productof the magnitude of the applied voltage and the holding time thereof.

[0210] The difference in drain current between the initial state and thestate with an applied voltage of +3 V held for 100 seconds is one ormore orders of magnitude upon the application of a voltage of +2 V,while being five or more orders of magnitude upon the application of avoltage of 0 V. Thus, if the semiconductor device of this embodiment isused as a memory, for example, multilevel information can be read out bydetecting the drain current.

[0211] In this manner, in the semiconductor device of this embodiment, along application of a voltage to the upper electrode 119 in a voltagerange in which the resistance value of the dielectric capacitor 104 canbe considered almost constant is used as write information, therebyallowing modulation of the characteristics of the MOS transistor suchthat the drain current increases with the applied voltage as compared tothe initial state. On the other hand, though not shown, if the state isheld at a negative voltage of −3 V, for example, the characteristics ofthe MOS transistor can be modulated such that a smaller amount of draincurrent flows upon the applied voltage than that in the initial state.

[0212] As described above, the semiconductor device of this embodimentcan perform a storing operation by a driving method completely differentfrom that for the known semiconductor device functioning as a multilevelmemory.

[0213] In addition, the semiconductor device of this embodiment has itscharacteristics changed, reflecting the history of earlier writteninformation. Therefore, the semiconductor device is applicable not onlyas a multilevel memory but also as a neuron element.

[0214] In the application as a neuron element, a plurality ofsemiconductor devices according to this embodiment are connected to eachother so that a load signal is applied to each interconnect 125 a and anoutput signal from a previous-stage neuron element is added to eachdrain region 103 a. At this time, if a voltage applied to theinterconnect 125 a is high and the pulse width thereof is long, currenteasily flows from the semiconductor devices. Such an application to aneuron element will be described in detail in a later embodiment.

[0215] In the semiconductor device of this embodiment, if an appliedvoltage of +3 V is hold for 100 seconds to create a state represented bythe B-C curve shown in FIG. 28, and then the interconnect 125 a, forexample, is grounded, the characteristic curve of this semiconductordevice gradually moves from the B-C curve toward the A-O curve and thenreturns to the A-O curve in approximately 100 seconds. This procedureshows a reverse operation of the storing operation for writteninformation and also shows that the device has a function of“forgetting” information once written with the passage of time. In apractical operation, since the device operates at high speed of 100 MHz,for example, such a “forgetting” function is effective in the case whereno signal is input for a long period. Specifically, the forgettingfunction makes an effective change in a portion which is seldom usedupon the input of a next leaning operation, thus improving a leaningfunction of the element.

[0216] In the semiconductor device of this embodiment, the amount of acharge accumulated in the intermediate electrode 114 and the gateelectrode 109 is adjusted depending on the time period over which theapplied voltage is held, thereby controlling flowability of the draincurrent. As in the case of the speed of writing information, the speedof forgetting can also be adjusted by controlling the magnitude of thepass current in a voltage range in which the pass current varies inproportion to the voltage.

[0217]FIG. 29 shows a correlation between a pass current flowing throughthe dielectric capacitor 104 of the semiconductor device of thisembodiment and a recovery time. In FIG. 29, the recovery time is a timeperiod over which the semiconductor device returns to the initial stateafter the application of a write voltage (i.e., time period required forforgetting information).

[0218]FIG. 29 shows that the recovery time tends to be shorter as thepass current increases in a voltage range in which the resistance valueof the dielectric layer 116 can be considered constant. From thistendency, it is shown that the charge accumulated in the intermediateelectrode 114 and the gate electrode 109 by the write voltage is leakingas a pass current.

[0219] In FIG. 29, in view of holding stored information, the passcurrent flowing upon the application of a voltage of 1 V to both ends ofthe capacitor 104 is set at 100 (mA/cm²) or less and the recovery timehas a holding time of 10 μsec. or more, such that a modulation memory ofthe transistor is held for a sufficiently long period relative to acomputation time. The pass current needs only to be sufficiently smallwith respect to a period over which data is to be held.

[0220] For example, in the semiconductor device of this embodiment, thepass current is about 10⁻⁸ (mA/cm²) upon the application of 1V as shownin the graph of FIG. 27. Therefore, the holding time is about 100seconds as shown in FIG. 29.

[0221] As described above, the semiconductor device of this embodimenthas a structure in which a dielectric capacitor and an electric resistorare disposed in parallel and connected to the gate electrode of a normalMOS transistor, thereby allowing the history of a signal to be stored asthe change in an applied voltage-drain current characteristic of the MOStransistor.

[0222] In addition, in the semiconductor device of this embodiment, thedielectric capacitor 104 and the resistor 106 are one and the same, thussimplifying the structure of the device. Thus, if the semiconductordevice of this embodiment is used as a memory cell by connecting thedrain region 103 a to a bit line and connecting the interconnect 125 ato a word line, for example, a multilevel memory having a small size canbe fabricated. Even if the semiconductor device of this embodiment isused as a neuron element, an advantage of allowing higher degree ofintegration is also obtained.

[0223] However, the information once stored is lost after a lapse of therecovery time. In view of this, the dielectric capacitor 104 and theresistor 106 may be fabricated separately and the resistor may be madeof a material through which a smaller amount of pass current flows.Then, information can be stored for a longer time.

[0224] In the semiconductor device of this embodiment, BST is used as adielectric material. Alternatively, the dielectric material may be anyother material so long as current flows through the film. As suchmaterials, strontium titanate, titanium oxide, tantalum oxide, aluminumoxide, zirconium oxide, cerium oxide, gadolinium oxide, lanthanum oxide,for example, are especially effective.

[0225] The distribution ratio of the voltage applied to the upperelectrode 119 between the dielectric capacitor and the MOS transistorvaries in inverse proportion to the capacitance of the capacitor. Thus,voltages distributed to the respective devices can be adjusted asrequired by changing the dielectric material, the area of the electrode,the thickness of the dielectric layer 116 or the gate insulating film,for example.

[0226] The gate insulating film of the MOS transistor is made of SiO₂ inthis embodiment. Alternatively, another insulator or dielectric such assilicon nitride may be used. Any type of field-effect transistor as wellas the MOS transistor may be used for the semiconductor device of thisembodiment. This is also applicable to the following embodiments.

[0227] In the semiconductor device of this embodiment, the write time is100 seconds under a condition that the applied voltage is +3 V. This isonly an example of a write time and does not mean that the amount of thecharge accumulated in the intermediate electrode is saturated. The timeperiod over which the charge is saturated is a little longer than 100seconds and will vary by changing the design of the device as describedabove. The write voltage is not limited to +3 V so long as theresistance value of the dielectric layer 116 is in a certain range. Ifthe write voltage is low, the time period required for writing becomeslonger.

[0228] In the semiconductor device of this embodiment, the resistancecomponent of the dielectric layer 116 in the dielectric capacitor 104also functions as the resistor 106. Alternatively, the dielectriccapacitor 104 and the resistor 106 may be provided separately from eachother. In such a case, although the area increases, design conditionscan be adjusted as required. For example, a leakage current from theresistor 106 is reduced or the time period required for writing isshortened, with the dielectric layer 116 and the resistor 106 made ofdifferent materials.

[0229] In the semiconductor device of this embodiment, a charge isaccumulated in the intermediate electrode 114 in proportion to theproduct of the applied voltage and the application time. Thus, if thedevice is applied to a neuron element, application time of a maximumvoltage is varied, thereby allowing weighting. In addition, a signalonce input is “forgotten” after the lapse of the recovery time unlessanother signal is input thereafter. As a result, for example, neuronelements used for computation are separated from unused neuron elements.That is to say, more effective computation is achieved over the longterm as compared to the known neuron element.

[0230] Embodiment 6

[0231] Next, a sixth embodiment of the present Invention will bedescribed with reference to the drawings.

[0232] In this embodiment, a method that is for driving the samesemiconductor device as in the fifth embodiment but is different fromthe method described in the fifth embodiment will be described. For thisreason, only a driving method for and operation of the semiconductordevice will be hereinafter described.

[0233]FIG. 30 is a graph showing a characteristic of a pass currentflowing between the intermediate electrode 114 and the upper electrode119 through the dielectric layer 116 when a voltage is applied betweenboth electrodes of the dielectric capacitor 140 including the dielectriclayer 116 of BST in the same semiconductor device as in the fifthembodiment shown in FIGS. 23 through 25.

[0234] In general, a perovskite oxide such as BST has a characteristicthat the resistance value is almost constant in a range in which theelectric field intensity is low, but when a voltage is furtherincreased, the pass current increases exponentially with a voltagehigher than about 1.3 V, as indicated by the characteristic curve shownin FIG. 30. Even in the negative range of the applied voltage, anapplied voltage-pass current characteristic is represented bysubstantially symmetric curves with respect to the axis of 0V.

[0235] This abrupt increase in the pass current can be explained as aSchottky current. Specifically, a barrier is present at the interfacebetween the intermediate or upper electrode 114 or 119 and thedielectric layer 116 so that current hardly flows while the electricfield intensity is below a certain degree. However, when the electricfield intensity exceeds the certain degree, current begins to flow overthe barrier. This current is called a Schottky current.

[0236] Hereinafter, a method for driving the semiconductor device ofthis embodiment utilizing such a characteristic of the dielectriccapacitor will be described.

[0237]FIG. 31 is a graph showing a drain current-applied voltagecharacteristic for explaining a driving method for and operation of thesemiconductor device of this embodiment. In FIG. 31, the applied voltageis a voltage applied between the interconnect 125 a (or the upperelectrode 119) and the substrate electrode 108.

[0238] The semiconductor device of this embodiment has a structure inwhich the MOS capacitor, in which the gate insulating film 107 issandwiched between the Si substrate 101 and the gate electrode 109, andthe dielectric capacitor, in which the dielectric layer 116 issandwiched between the intermediate electrode 114 and the upperelectrode 119, are connected in series. Thus, the applied voltage isdistributed to the respective capacitors. For example, when the appliedvoltage is +2 V, the applied voltage is distributed to 1.5 V and 0.5 V,which are applied to the MOS capacitor and the dielectric capacitor,respectively. When the applied voltage is +8 V, the applied voltage isdistributed to 6.0 V and 2.0 V, which are applied to the MOS capacitorand the dielectric capacitor 104, respectively. As shown in FIG. 30, thedielectric capacitor 104 of this embodiment operates as a resistorhaving a substantially constant resistance value upon the application ofa voltage of 0.5 V, while operating a resistor in which the resistor isa relatively small, i.e., current increases exponentially with theincrease in voltage, upon the application of a voltage of 2.0 V.

[0239] In the method for driving the semiconductor device of thisembodiment, a voltage at about 50 kHz, for example, is applied so as tooperate the semiconductor device.

[0240] First, in the initial state, supposing the applied voltage is inthe range of ±2 V, the semiconductor device of this embodiment exhibitsa characteristic moving along a characteristic curve including thepoints D and O′ (hereinafter referred to as a D-O′ curve) in FIG. 31. Inthe range not higher than about 0 V, though the D-O′ curve is not showntherein, a drain current is at a noise level, i.e., at a levelsufficiently smaller than 10⁻⁸ (A).

[0241] In this state, when a voltage of 2 V is applied, for example, adrain current of about 6×10⁻⁴ flows (the point D). Then, when a voltageof 0 V is applied, the drain current returns to the state indicated bythe point O at which only current almost at a noise level flows. Even ifa voltage of 2 V or less is applied and then a voltage of 0 V isapplied, the drain current is substantially at a noise level. That is tosay, the semiconductor device of this embodiment operates as the MOStransistor at the applied voltage in the range of −2 V to +2 V.

[0242] Then, when a high voltage of +8 V is applied, for example, thepass current flowing through the dielectric layer 116 increasesexponentially, so that a charge is accumulated in the intermediateelectrode 114 and the gate electrode 109 in a very short time. In thisembodiment, the device operates with the frequency of a pulse voltage tobe applied set at 50 kHz. Alternatively, if a pulse voltage of +8 V isapplied for 20 μsec., it is possible to shift the characteristic to thecurve including points E and F shown in FIG. 31. That is to say, if theapplied voltage is increased, the VG-ID characteristic of the MOStransistor can be changed in a short time. The time period required foraccumulating a charge is 100 seconds in the fifth embodiment. On theother hand, according to the driving method of this embodiment, the timeperiod is greatly shortened, i.e., 20 μsec.

[0243] Hereinafter, the operation of the semiconductor device of thisembodiment will be described in further detail. When a pulse voltage of+8 V is applied, the pass current flowing through the dielectric layer116 increases exponentially, so that a charge is accumulated in theintermediate electrode 114 and the gate electrode 109 rapidly.

[0244] Thereafter, when the applied voltage is returned to 0V, thecharacteristic changes into the state represented by the point F in FIG.31 so that the drain current varies. When a voltage of +2 V is furtherapplied to the upper electrode 119, the characteristic changes from thestate at the point F to the state at the point E, so that the a draincurrent of about 3×10⁻³ (A) flows. However, when the applied voltage isset at 0V again, the characteristic returns to the state at the point F.That is to say, even if a low pulse voltage of about 0V to 2 V isapplied after the input of a high pulse voltage, the draincurrent-applied voltage characteristic of the semiconductor device doesnot change. On the other hand, when a negative pulse voltage of −2 V isapplied to the upper electrode 119 in the state indicated by the pointF, the state of the semiconductor device moves to a point G, so that thedrain current decreases by about one order of magnitude. When theapplied voltage is then set at 0V again, the state moves to a point H,which is close to the point F and at which the drain current is slightlysmaller than in the state at the point F but the drain current does notchange largely.

[0245] Based on the same principle, a voltage of −8 V is applied, forexample, the characteristic of the device naturally changes into thestate in which the drain current varies very slightly with a scan of ±2V upon the application of the voltage of −8 V.

[0246] As described above, according to the method for driving thesemiconductor device in this embodiment, information is written in avoltage range in which the pass current flowing through the dielectriccapacitor 104 increases exponentially with the rise of the appliedvoltage. In reading out the information, for example, the MOS transistoris driven in a voltage range in which the pass current variessubstantially in proportion to the applied voltage. With this method,the time period required for writing information can be greatly shorten,as compared to the method for driving the semiconductor device describedin the fifth embodiment.

[0247] By the method for driving the semiconductor device in thisembodiment, the history of earlier written information can be stored asvariations in device characteristics. Therefore, the semiconductordevice of this embodiment can be applied not only as a multilevel memorybut also as a neuron element. If the device is used as a neuron element,the time period required for writing information can be greatlyshortened as compared to the method in the fifth embodiment, thusimproving the computation speed largely.

[0248] Unlike the method of the fifth embodiment, the method for drivingthe semiconductor device in this embodiment is characterized in that theVG-ID characteristic of the MOS transistor can be changed not using thelength of an applied voltage pulse but using the magnitude of theabsolute value of the applied voltage. That is to say, the VG-IDcharacteristic can be modulated by setting only the value of the pulsevoltage to be applied with the pulse thereof set periodic.

[0249] In the method for driving the semiconductor device of thisembodiment, the write voltage is 8 V. Alternatively, the writingoperation may be performed at higher voltages. However, even when thevoltage applied to the interconnect 125 a or the upper electrode 119 isless than 8 V, for example, the write time can be shortened by reducingthe capacitance of the dielectric layer through the process of reducingthe area of the dielectric capacitor, the process of increasing thethickness of the dielectric layer, or other suitable processes, andeventually increasing the voltage to be distributed to the dielectriccapacitor.

[0250] In the method for driving the semiconductor device of thisembodiment, the interconnect 125 a, for example, is grounded, so thatthe state of the semiconductor device returns to the initial staterepresented by the D-O′ curve in FIG. 31 with a lapse of time. That isto say, the semiconductor device of this embodiment has a function of“forgetting”, as described in the fifth embodiment.

[0251] In the method for driving the semiconductor device of thisembodiment, in view of holding stored information, the pass currentflowing upon the application of a voltage of 1 V to both ends of thedielectric capacitor 104 is set at 100 (mA/cm²) or less and the recoverytime has a holding time of 10 μsec. or more. This is distinguished fromthe case where a pulse voltage having a large absolute value is applied.The method is conducted under the same conditions as in the fifthembodiment, so that the time period required for recovery is about 100seconds in this embodiment.

[0252] Embodiment 7

[0253] A semiconductor device according to a seventh embodiment of thepresent invention is the same as the semiconductor device of the sixthembodiment, except for part of the structure, a driving method for andoperation of the device.

[0254]FIG. 32 is an equivalent circuit diagram showing the semiconductordevice of this embodiment. As shown in FIG. 32, the semiconductor deviceof this embodiment is characterized by having a structure in which adielectric capacitor 104 a and a resistor 106 are disposed in paralleland connected to a gate electrode 109 of a field-effect transistor(hereinafter referred to an MOS transistor).

[0255] The semiconductor device of this embodiment has substantially thesame structure as those of the devices in the fifth and sixthembodiments but is different from the devices in that a ferroelectriclayer 131 of a ferroelectric material is used instead of the dielectriclayer 116.

[0256] Specifically, the semiconductor device of this embodimentincludes: a control-voltage supply unit 110; an MOS transistor includingthe gate electrode 109, drain and source regions 103 a and 103 b and asubstrate electrode 108; the ferroelectric capacitor 104 a; and theresistor 106. The ferroelectric capacitor 104 a and the resistor 106 aredisposed in parallel and interposed between the gate electrode 109 ofthe MOS transistor and the control-voltage supply unit 110. Theferroelectric capacitor 104 a includes: an upper electrode 119; anintermediate electrode 114; and a ferroelectric layer 131 of bismuthtitanate (BIT) sandwiched between the upper electrode 119 and theintermediate electrode 114 and having a thickness of 300 nm. In thesemiconductor device of this embodiment, the ferroelectric layer 131also functions as the resistor 106. The source region 103 b and thesubstrate electrode 108 are connected to each other.

[0257]FIGS. 33A through 33D are cross-sectional views showing respectiveprocess steps for fabricating the semiconductor device of thisembodiment. In FIGS. 33A through 33D, the same components as those shownin FIGS. 26A through 26D are identified by the same reference numerals.

[0258] First, in a process step shown in FIG. 33A, through the sameprocedure as in the fifth embodiment, an isolation oxide film 105 isformed in a Si substrate 101 by a LOCOS process. Thereafter, a SiO₂ filmhaving a thickness of 5 nm is formed by a pyrogenic oxidation performedon the substrate, and then polysilicon containing an n-type impurity isdeposited over the SiO₂ film. Then, the polysilicon layer and the SiO₂film are patterned, thereby forming a gate electrode 109 and a gateinsulating film 107, respectively, over the Si substrate 101.Subsequently, a p-type impurity such as boron is implanted into the Sisubstrate 101, thereby forming drain and source regions 103 a and 103 bto the sides of the gate electrode 109. The MOS transistor fabricated inthis process step has a gate length of 1 μm and a gate width of 10 μm.

[0259] Next, in a process step shown in FIG. 33B, through the sameprocedure as in the fifth embodiment, after a first interleveldielectric film 111 of SiO₂ has been formed over the substrate, contactholes are formed by dry etching using a resist mask and then are filledwith polysilicon, thereby forming plug interconnects 113 a, 113 b and113 c of polysilicon, respectively. Thereafter, an intermediateelectrode 114 connected to the gate electrode 109 via the pluginterconnect 113 a, a pad 115 a connected to the drain region 103 a viathe plug interconnect 113 b, and a plug interconnect 15 b connected tothe source region 103 b via the plug interconnect 113 c, are formed. Thecomponents are respectively made of the same materials as correspondingones in the fifth embodiment. However, the intermediate electrode has asize of 1 μm×2 μm, which is one-fifth of the area of the MOS transistor.

[0260] Then, in a process step shown in FIG. 33C, BST is deposited by asputtering process under conditions that the substrate temperature is600° C., the partial pressure of oxygen is 20% and the RF power is 100W,thereby forming a first ferroelectric layer 131 having a thickness of300 nm over the substrate. Thereafter, through the same procedure as inthe fifth embodiment, an upper electrode 119 is formed on part of theferroelectric layer 131, facing the intermediate electrode. The upperelectrode 119 has a size of 1 μm×2 μm, which is the same as the size ofthe intermediate electrode 114 and one-fifth of the area of the MOStransistor.

[0261] Then, in a process step shown in FIG. 33D, through the sameprocedure as in the first embodiment, a second interlevel dielectricfilm 121 is formed on the ferroelectric layer 131. Subsequently, aninterconnects 125 a, 125 b and 125 c are formed on the second interleveldielectric film 121 to reach the upper electrode 119, the pad 115 a andthe pad 115 b, respectively.

[0262] In the semiconductor device of this embodiment fabricated by themethod described above, the ferroelectric capacitor 104 a and theresistor 106 are one the same, and the resistor 106 is a resistancecomponent of the ferroelectric capacitor 104 a.

[0263] Therefore, the structure shown in FIG. 32 can be achieved in arelatively small area. In addition, the number of fabrication processsteps is smaller than in the case where the ferroelectric capacitor 104a and the resistor 106 are fabricated separately.

[0264] Hereinafter, a driving method for and operation of thesemiconductor device of this embodiment will be described.

[0265]FIG. 34A shows an equivalent circuit in a coarse control in whichstored information is changed largely in the semiconductor device ofthis embodiment. FIG. 34B shows an equivalent circuit in a fine controlin which stored information is changed slightly in the semiconductordevice of this embodiment. FIG. 35 is a graph showing a characteristicof a pass current when a voltage is applied to both ends of theferroelectric capacitor 104 a. In this embodiment, the pass current is acurrent flowing between the intermediate electrode 114 and the upperelectrode 119 through the ferroelectric layer 131.

[0266] In this embodiment, an oxide, e.g., BIT used as a ferroelectricmaterial, whose elements have a composition represented as ABO₃ andwhose crystal structure has a perovskite structure, exhibits thefollowing characteristic, as BST used in the first and sixthembodiments. Specifically, the resistance value thereof is so small thatit may be ignored while an applied electric field intensity is small.When the voltage is further increased, the pass current increasesexponentially. FIG. 35 shows that the pass current also increasesexponentially upon the application of a voltage higher than about 1.8 Vin the ferroelectric capacitor 104 a of this embodiment. When a negativevoltage is applied, the characteristic is represented by substantiallysymmetric curves with respect to the axis of 0V.

[0267] Therefore, as shown in FIG. 35, when a voltage distributed to theferroelectric is in a coarse control, i.e., not higher than −2.3 V ornot lower than +2.3 V, the ferroelectric also functions as the resistor106, so that a leakage current I flows. In this case, the equivalentcircuit has a configuration in which the ferroelectric capacitor 104 aand the resistor 106 are disposed in parallel and connected to the gateelectrode 109 of the MOS transistor, as shown in FIG. 34A.

[0268] On the other hand, when a voltage distributed to theferroelectric is in a fine control, i.e., in the range of −1.4 V to +1.4V, both inclusive, current hardly flows in the ferroelectric so that theferroelectric functions as an insulator. In this case, the equivalentcircuit has a configuration in which only the ferroelectric capacitor104 a is connected to the gate electrode 109 of the MOS transistor, asshown in FIG. 34B.

[0269] The semiconductor device of this embodiment has a structure inwhich the MOS capacitor, in which the gate insulating film 107 issandwiched between the Si substrate 101 and the gate electrode 109, andthe ferroelectric capacitor, in which the ferroelectric layer 131 issandwiched between the intermediate electrode 114 and the upperelectrode 119, are connected in series. Thus, the applied voltage isdistributed to the respective capacitors. For example, when a voltage of+2 V is applied to the entire device, the applied voltage is distributedto 1.2 V and 0.8 V, which are applied to the MOS transistor and theferroelectric capacitor 104 a, respectively. When the applied voltage is+6 V, the applied voltage is distributed to 3.6 V and 2.4 V, which areapplied to the MOS transistor and the ferroelectric capacitor 104 a,respectively.

[0270] In the semiconductor device of this embodiment, if the voltage tobe distributed to the ferroelectric capacitor 104 a is set in the coarsecontrol range, the leakage current can be increased and the potential atthe floating gate (i.e., the gate electrode 109) can be changed largely.If the voltage to be distributed to the ferroelectric capacitor 104 a isset in the fine control range, the leakage current can be reduced,information can be stored, and the potential at the floating gate can befinely adjusted by changing the polarization of the ferroelectric.

[0271]FIG. 36 is a graph showing an example of an actual method forapplying a voltage based on the findings described above. In thisexample, a pulse voltage of 2.5 V is applied to the ferroelectric in aninitial period of 1 μsec. This allows a charge to be accumulated in thefloating gate through the ferroelectric at high speed. During thisperiod, the ferroelectric is polarized in one direction.

[0272] Next, after 5 μsec., a small negative voltage is applied to theferroelectric for 1 μsec. During this period, the leakage current fromthe ferroelectric is so small that it may be neglected, resulting inthat the polarization of the ferroelectric is gradually inverted littleby little. In this manner, the amount of the charge accumulated in thefloating gate can be varied slightly.

[0273] In a general ferroelectric gate transistor, the amount of chargein the floating gate can be varied only by the polarization value of theferroelectric. On the other hand, if the driving method of thisembodiment is used, the amount of the charge can be varied in a verywide range. Specifically, an ON resistance value of the MOS transistorcan be determined in a very wide range and in detail. This means thatthe device of this embodiment functions as an analog memory in whichmultilevel information can be continuously stored according to theamount of the charge accumulated in the floating electrode.

[0274]FIG. 37 is a characteristic graph for describing operation of thesemiconductor device of this embodiment in the initial state. In FIG.37, the abscissa represents an applied voltage, while the ordinaterepresents a drain current. In this graph, the applied voltage indicatesa voltage applied between the interconnect 125 a (or the upper electrode119) and the Si substrate 101.

[0275] As shown in FIG. 37, when a voltage in the range of ±2 V isapplied to the semiconductor device of this embodiment in the initialstate, the VG-ID characteristic of the MOS transistor in the deviceexhibits a hysteresis moving counterclockwise. That is to say, thesemiconductor device of this embodiment operates as a so-calledferroelectric gate transistor.

[0276] Therefore, even when a voltage of +2 V is applied to thesemiconductor device and then removed, for example, a charge is inducedinto the intermediate electrode 114 due to the polarization of theferroelectric layer 131, thus causing a potential. Thus, a drain currentof about 2 μA flows even upon the application of a voltage of 0 V. Onthe other hand, when a voltage of −2 V is applied and then removed, thedrain current becomes extremely small (i.e., 10⁻⁸ A or less, not shown)conversely. In this case, the voltage between source and drain is also 1V, as in the fifth embodiment.

[0277] If a voltage of +6 V is then applied to the semiconductor deviceof this embodiment, the drain current can be set at another value.

[0278]FIG. 38 is a graph showing a drain current when a pulse voltage of2 V is repeatedly applied to the semiconductor device of this embodimentto which a write voltage of +6 V has been applied. The interval of thepulse voltage in this graph is 20 μsec.

[0279] As shown in FIG. 38, when a write voltage of +6 V is applied tothe semiconductor device of this embodiment in the initial state, avoltage of 2.4 V is distributed to the ferroelectric capacitor, so thatthe pass current increases exponentially. Accordingly, a charge isaccumulated in the intermediate electrode 114 and the gate electrode 109so that the drain current increases by more than two orders ofmagnitude. Even if the same pulse voltage of +2 V is input thereafter,the device exhibits the characteristic that the drain current hardlyvaries and is about 1×10⁻³ (A).

[0280] This graph shows that data can be stored in the semiconductordevice of this embodiment with stability by applying a high writevoltage thereto.

[0281]FIG. 39 is a graph showing an applied voltage-drain currentcharacteristic of the semiconductor device of this embodiment whenscanned in the applied-voltage range of ±2 V after the application of+6V.

[0282] First, when a voltage of +6 V is applied to the semiconductordevice and then is removed, the drain current takes a value indicated bya point I in FIG. 39.

[0283] Next, when a voltage of 2 V is applied to the semiconductordevice in the state indicated by the point I and then the voltage isremoved, the drain current describes a trajectory from the point I to apoint J shown in FIG. 39. After the removal of the voltage, the draincurrent returns to the point I. The state indicated by the point Icorresponds to the state in which a pulse voltage is applied as shown inFIG. 38.

[0284] If a voltage of −2 V is applied to the semiconductor device inthe state indicated by the point I, the drain current moves to the pointK, i.e., decreases by about two orders of magnitude to be 1×10⁻⁵ (A) orless. Subsequently, when the voltage is removed, the drain current movesto a point L, i.e., decreases by about one order of magnitude ascompared to the state at the point I before the application of thevoltage.

[0285] In the semiconductor device of the sixth embodiment, there is nosubstantial difference in the drain current between the point F and apoint H in FIG. 31. This makes the semiconductor device of thisembodiment differ largely from the semiconductor devices of the fifthand sixth embodiments.

[0286] In this manner, the semiconductor device of this embodiment canhold more data than the semiconductor devices of the fifth and sixthembodiments.

[0287] Then, when a voltage of ±2 V is applied to the semiconductordevice in the state indicated by the point L in FIG. 39, the draincurrent moves to a point M. When the voltage is then removed, the draincurrent moves to a point N. In this case, the drain current varies, asdescribing the trajectory indicated by the points L→M→N, so that thedrain current at the point N is larger than that at the previous pointL. Thus, by thus scanning using a small applied voltages of ±2 V afterthe application of a high voltage of +6 V, the drain current can befurther modulated.

[0288] On the other hand, a high negative pulse voltage may be input asa write voltage.

[0289]FIG. 40 is a graph showing a drain current in the case where avoltage of −6 V is applied to the semiconductor device of thisembodiment before a pulse voltage of +2 V is applied and then removed.The pulse interval of the pulse voltage is 20 μsec.

[0290] As shown in FIG. 40, by applying a voltage of −6 V to thesemiconductor device of this embodiment in the initial state, the draincurrent at 0 V is four orders of magnitude smaller than that in theinitial state. In this case, the variations in the drain current aresmall when a pulse voltage of +2 V is repeatedly applied and removed.

[0291]FIG. 41 is a graph showing an applied voltage-drain currentcharacteristic of the semiconductor device of this embodiment whenscanned in the applied-voltage range of ±2 V after the input of a pulsevoltage of −6 V. Though hysteresis is also observed in this state at anapplied voltage of 0V, the drain current is extremely low even upon theapplication of a voltage with each polarity. By thus applying a negativevoltage, a small drain current, which is distinguished from that in thecase of application of a positive voltage, is obtained.

[0292] As described above, in the semiconductor device of thisembodiment, operations of driving the MOS transistor in a voltage rangein which a resistance component of the ferroelectric capacitor 104 a hasa substantially constant resistance value (a low voltage range), and ofwriting in a range in which a current flowing through the ferroelectriccapacitor 104 a increases exponentially, are properly used.

[0293] In the semiconductor device of this embodiment, the change in theapplied voltage-drain current characteristic depends on the change inthe VG-ID characteristic of the MOS transistor which is caused byaccumulating a charge in the intermediate electrode 114 through theferroelectric layer 131 and thereby accumulating a charge also in thegate electrode 109 of the MOS transistor. Especially, in thesemiconductor device of this embodiment, the amount of the chargeaccumulated in the intermediate electrode and the gate electrode 109 canbe changed depending on the direction of polarization of theferroelectric 104 a. Thus, the semiconductor device of this embodimentis usable as a multilevel memory which can take much more levels thanthe semiconductor devices of the fifth and sixth embodiments.

[0294] A large modulation of the drain current caused by a high pulsevoltage and a small modulation of the drain current caused by a lowpulse voltage can be respectively reflected as modulations of the draincurrent. Therefore, the semiconductor device of this embodiment isapplicable as a neuron element with extremely high flexibility inweighting.

[0295] As the semiconductor devices of the fifth and sixth embodiments,the semiconductor device of this embodiment also has a function of“forgetting” by making the interconnect 125 a to be grounded, forexample, and thereby restoring the characteristic to the initial state.

[0296] In the semiconductor device of this embodiment, to hold storedinformation, the pass current flowing upon the application of a voltageof 1 V to both ends of the ferroelectric capacitor is set equal to orsmaller than 100 (mA/cm²) and the recovery time is set equal to orlonger than 10 μsec., thus making a clear difference between themodulation of the drain voltage caused by the polarization of theferroelectric and the modulation in the device of this embodiment. Thistendency is substantially the same as in the semiconductor device of thefifth embodiment shown in FIG. 29. The time period required for recoveryis about 100 seconds.

[0297] In the semiconductor device of this embodiment, the ferroelectriclayer 131 and the resistor 106 may be separately provided, as in thesemiconductor device of the fifth embodiment. In such a case, to extendthe time period required for holding information, for example, thesemiconductor device can be designed properly to meet requirements bymaking the resistor 106 out of a ferroelectric material that is lessconductive than a ferroelectric material constituting the ferroelectriclayer 131.

[0298] In the case where the ferroelectric layer 131 and the resistor106 are provided separately, a dielectric may be used as a material forthe resistor 106.

[0299] In the method for driving the semiconductor device of thisembodiment, a voltage range in which the ferroelectric layer has asubstantially constant resistance value and a voltage range in which thepass current increases exponentially with the voltage are properly used.If the semiconductor device is driven only in a narrow voltage range inwhich the resistance value of the ferroelectric layer is so small thatit may be neglected and the pulse width of the applied voltage is setsufficiently shorter than the recovery time, as in the fifth embodiment,the amount of the charge accumulated in the intermediate electrode 114and the gate electrode 109 can be varied, as in the fifth embodiment.

[0300] In the semiconductor device of this embodiment, BIT is used as amaterial for the ferroelectric layer. Alternatively, other materialsexhibiting similar ferroelectric properties such as lead titanate, leadzirconate titanate or strontium tantalite may be used as a material forthe ferroelectric layer.

[0301] Embodiment 8

[0302] In a semiconductor device according to an eighth embodiment ofthe present invention, the resistor 106 of the seventh embodiment isreplaced by a resistor 150, which is a variable resistor (a varistor)and is made of zinc oxide (ZnO). The resistor 150 and a ferroelectricare provided separately.

[0303]FIG. 42A is a circuit diagram showing the semiconductor device ofthis embodiment. FIG. 42B is a graph showing a varistor characteristicof the resistor 150. Components already shown in FIG. 32 are indicatedby the same reference numerals.

[0304] As shown in FIG. 42B, some metal oxides such as ZnO have acharacteristic that the resistance value changes largely with an appliedvoltage. Specifically, the resistor 150 of this embodiment having anelectrode area of 10 μm² exhibits a resistance value of as much as about180 GΩ in the voltage range of −1 V to +1 V, both inclusive, while theresistance value decreases drastically when the absolute value of thevoltage exceeds 1.5 V.

[0305] Thus, if the voltage ranges not more than −2 V and not less than+2 V are taken as a coarse control voltage range and the range of −1 Vto +1 V, both inclusive, is taken as a fine control voltage range, thesemiconductor device can operate as the semiconductor device of theseventh embodiment.

[0306] In addition, in the semiconductor device of this embodiment, theresistor 150 may be made of any material, so that the range of anoperating voltage can be set flexibly. For example, the voltagecorresponding to the low resistance state of the resistor 150 is setslightly higher than the voltage at which the polarization of theferroelectric is saturated, for example, a coarse control and a finecontrol can be performed at lower driving voltages.

[0307]FIG. 43 is a cross-sectional view showing a structure of thesemiconductor device of this embodiment.

[0308] As shown in FIG. 43, a ferroelectric 131 and the resistor 150 ofthis embodiment may share upper and lower electrodes. Such a structurecan be easily attained by using publicly known techniques. For example,a ferroelectric is deposited over the entire surface of a lowerelectrode and is selectively etched in part, and then, ZnO is depositedover part of the lower electrode where the ferroelectric has beenremoved. FIG. 43 shows an example in which the ferroelectric and theresistor are in contact with each other. Alternatively, theferroelectric and the resistor may be apart from each other.

[0309] The resistor may be made of a perovskite oxide such asBa_(x)Sr_(1-x)TiO₃, a TiO₂-based oxide, a Fe₂O₃-based oxide, or aCu₂O-based oxide as well as ZnO. Ba₂O₃ or a rate-earth element may beadded to the metal oxide described above so as to reduce the resistanceof the metal oxide. Then, the resistivity and a rate of change inresistance of the metal oxide material can be controlled as required. AP-N junction of Si, an Al-added SiC semiconductor, Se, and the like maybe used as a material for the resistor.

[0310] In the semiconductor device of this embodiment, a coarse controland a fine control are used properly so as to hold multilevelinformation excellently. An element connected in parallel with theferroelectric is not limited to a resistor but may be any other elementor circuit so long as a charge to be accumulated in a floating gate canbe controlled by an applied voltage.

[0311] Embodiment 9

[0312] In a semiconductor device according to a ninth embodiment of thepresent invention, the resistor 106 of the seventh embodiment isreplaced by two diodes connected in parallel with each other anddisposed in opposite orientations.

[0313]FIG. 44 is a circuit diagram showing the semiconductor device ofthis embodiment. Components already shown in FIG. 32 are indicated bythe same reference numerals.

[0314] As shown in FIG. 44, the semiconductor device of this embodimentincludes: a control-voltage supply unit 110; an MOS transistor; aferroelectric capacitor 104 a; a diode 152; and a diode 154. Theferroelectric 104 and the diodes 152 and 154 are connected to a gateelectrode 109 of the MOS transistor and arranged in parallel. The diodes152 and 154 are disposed in opposite orientations. That is to say, therespective input ports of the diodes 152 and 154 are connected torespective output ports.

[0315] In this embodiment, the diodes 152 and 154 are PN diodes, forexample. When a forward voltage at a given level or higher is applied tothese diodes, current flows, while current hardly flows upon theapplication of a voltage lower than the given level. Below a breakdownvoltage, current hardly flows even upon the application of a reversevoltage.

[0316] As shown in FIG. 44, by connecting the two diodes in oppositeorientations in parallel, current hardly flows in the voltage range of−t V to +t V, both inclusive, while current flows when the absolutevalue of the voltage is t V or higher, allowing a charge to be flowninto the floating gate (where the threshold voltage of the diodes is tV).

[0317] Thus, as in the third and eighth embodiments, multilevel data canbe stored, taking a range in which the absolute value of the distributedvoltage is high as a coarse control, and a range in which the absolutevalue of the distributed voltage is small as a fine control.

[0318] In the semiconductor device of this embodiment, PN diodes areused as the diodes 152 and 154. Alternatively, any other diode such as aSchottky diode may be used instead.

[0319] Embodiment 10

[0320] In a semiconductor device according to a tenth embodiment of thepresent invention, the resistor 106 of the seventh embodiment isreplaced by an MIS transistor which is turned ON or OFF by a controlvoltage Vr.

[0321]FIG. 45 is a circuit diagram showing the semiconductor device ofthis embodiment.

[0322] As shown in FIG. 45, the semiconductor device of this embodimentincludes: a control-voltage supply unit 110; an MOS transistor; aferroelectric capacitor 104 a connected to a gate electrode 109 of theMOS transistor; an MIS transistor 156 interposed between thecontrol-voltage supply unit 110 and the gate electrode 109. The MIStransistor 156 is controlled by a control voltage Vr.

[0323] In the semiconductor device of this embodiment, the MIStransistor 156 is appropriately turned ON or OFF by an external controlcircuit or the like, so that a coarse control or a fine control of thepotential at the floating gate can be used properly as described in thethird through fifth embodiments. For example, when the absolute value ofthe voltage applied to the MOS transistor is equal to or higher than agiven value, the MIS transistor 156 is turned ON. When the absolutevalue of the voltage applied to the MOS transistor is lower than thegiven value, the MIS transistor 156 is turned OFF.

[0324] In the semiconductor device of this embodiment, a coarse controland a fine control can be switched by changing the control voltage Vrwithout depending on the structure of the MIS transistor. Thus, thedevice can be operated in an arbitrary voltage range.

[0325] In the semiconductor device of this embodiment, a bipolartransistor may be used instead of the MIS transistor 156.

[0326] Embodiment 11

[0327] In a semiconductor device according to an eleventh embodiment ofthe present invention, the resistor 106 of the seventh embodiment isreplaced by a variable resistance element 158 whose crystallinity iscontrolled by a resistance control signal Vw.

[0328]FIG. 46 is a circuit diagram showing the semiconductor device ofthis embodiment.

[0329] As shown in FIG. 46, the semiconductor device of this embodimentincludes: a control-voltage supply unit 110; an MOS transistor; aferroelectric capacitor 104 a interposed between the control-voltagesupply unit 110 and a gate electrode 109 of the MOS transistor; and thevariable resistance element 158 interposed between the control-voltagesupply unit 110 and the gate electrode 109 of the MOS transistor andarranged in parallel with the ferroelectric 104 a. The variableresistance element 158 is made of an alloy containing three elements ofgermanium (Ge), tellurium (Te) and antimony (Sb), for example, as maincomponents. The crystallinity of the variable resistance element 158 iscontrolled by a resistance control signal Vw.

[0330] The variable resistance element 158 is in an amorphous state whenthe resistance control signal Vw has a high voltage pulse of a givenvalue or higher, so that the resistance value is high. When the Vw pulseis then reduced, the resistance value decreases gradually to be adjustedto an arbitrary value. Thus, in accumulating a charge in the floatinggate, a voltage is supplied from the control-voltage supply unit 110with the Vw pulse set at a low voltage. In a fine control of thepotential at the floating gate or in holding data, the Vw pulse is setat a high voltage, and a voltage in a fine control voltage range shownin FIG. 35 is applied to the ferroelectric capacitor 104 a. Then, aleakage current from the ferroelectric as well as a leakage current fromthe variable resistance element can be reduced. By thus using thevariable resistance element, a semiconductor device in which multilevelinformation can be stored excellently is implemented.

[0331] The variable resistance element 158 of this embodiment ispreferably made of a chalcogenide material other than Ge, Te and Sb.

[0332] Embodiment 12

[0333] As a twelfth embodiment of the present invention, a neurocomputerin which the semiconductor device of the seventh embodiment is used as aneuron element according to will be described.

[0334]FIG. 48 is a diagram showing a model representing a simplifiedstructure of a fundamental unit of the brain of an animal. As shown inFIG. 48, the brain of an animal includes: a previous-stage neuron 141 aand subsequent-stage neurons 141 b and 142 c that are nerve cells havinga computation function, nerve fibers 142 a, 142 b and 142 c transmittingcomputation results from neurons; and synaptic connections 143 a, 143 band 143 c which add weights to signals transmitted through the nervefibers and which input the signals to the neurons.

[0335] Specifically, a signal transmitted through a large number ofnerve fibers including the nerve fiber 142 a receives weights such asweights Wa, Wb and Wc at a large number of synaptic connectionsincluding the synaptic connection 143 a and then is input to the neuron141 a. At the neuron 141 a, a linear sum of the strengths of inputsignals is taken. When the sum exceeds a threshold value, the neuron 141a is activated to output a signal to the nerve fiber 142 b. The actionof outputting a signal upon the activation of a neuron is called“firing” of the neuron.

[0336] The output signal is divided into two, for example. Each of thedivided signals receives a weight at a synaptic connection and theninput to the subsequent-stage neuron 141 b or 141 c. At thesubsequent-stage neuron 141 b or 141 c, a linear sum of input signals isalso taken. When the sum exceeds a threshold value, the subsequent-stageneuron 141 b or 141 c is activated and outputs a signal. This operationis repeated at a plurality of stages, thereby outputting a computationresult.

[0337] Loads added to the synaptic connections are gradually modifiedthrough leaning, so that an optimum computation result is finallyobtained.

[0338] The neurocomputer is designed to use semiconductor devices forexecuting such a function of the brain.

[0339]FIG. 47 is a diagram schematically showing a fundamental structureof the neurocomputer of this embodiment. In FIG. 47, components alreadymentioned for the semiconductor device of the seventh embodiment areidentified by the same reference numerals shown in FIG. 32.

[0340] As described above, the semiconductor device of the seventhembodiment for use in the neurocomputer of this embodiment includes: acontrol-voltage supply 110; an MOS transistor Tr11 including a gateelectrode 109, drain and source regions 103 a and 103 b and a substrateelectrode 108; a ferroelectric capacitor 104 a; and the resistor 106.The ferroelectric capacitor 104 a and the resistor 106 are disposed inparallel and interposed between the gate electrode 109 of the MOStransistor Tr11 and the control-voltage supply unit 110.

[0341] As shown in FIG. 47, the neurocomputer of this embodimentincludes: the semiconductor device of the seventh embodiment; anelectric resistance 133 interposed between the earth and a sourceelectrode of the MOS transistor Tr11; a node N1 disposed between thesource electrode of the MOS transistor Tr11 and the electric resistance133; a transistor Tr12 including a floating gate, a large number ofinput gates arranged on the floating gate and source and drainelectrodes; and an electric resistance 132 interposed between the sourceelectrode of the transistor Tr12 and a voltage supply line Vdd. Thesource electrode of the transistor Tr12 is grounded to the earth. Thenode N1 is connected to one of the input gates.

[0342] The semiconductor device of the seventh embodiment, the node N1and the electric resistance 133 correspond to synapse units (connectionsbetween nerve fibers and synapses) of the brain of an animal thattransmit signals and add weights. A large number of synapse units areconnected to a neuron unit (a neuron MOS) constituted by the transistorTr12 and the electric resistance 132. The neurocomputer of thisembodiment mimics the behavior of the brain and has a structure formedby stacking almost four layers, each of which is made of a synapse unitand a neuron unit connected to each other.

[0343] Hereinafter, a signal-flow path will be described. First, anoutput signal Ss1 from a previous-stage neuron unit is input to a drainelectrode of the MOS transistor Tr11, and a load signal S₁ is input tothe control-voltage supply unit 110. Then, the value of a drain currentflowing from the MOS transistor Tr11 varies according to the load signalS₁.

[0344] Then, a current signal output from the MOS transistor Tr11 isconverted into a voltage signal by the electric resistance 133, and isinput to one of the input gates of the transistor Tr12. Signals from alarge number of other synapse units are also input to the input gates ofthe transistor Tr12. When the sum of the voltages of these input signalsexceeds the threshold value of the transistor Tr12, the neuron unit“fires” to output a signal therefrom. Subsequently, the output signal istransmitted to a subsequent-stage synapse unit.

[0345] On the other hand, if the sum of the voltages of the inputsignals from the synapse units is smaller than the threshold value ofthe transistor Tr12, no signal is output.

[0346] Since the semiconductor device of the seventh embodiment in whichmultilevel information can be stored at a synapse unit with a simplestructure is used for a synapse unit in the neurocomputer of thisembodiment, various weights can be added to signals within a small area.As a result, the neurocomputer in which synapse units and neuron unitsare integrated and which has a leaning function can be downsized.

[0347] In the semiconductor device of the seventh embodiment, asdescribed above, the applied voltage-drain current characteristic ischanged at a voltage of about 6V, and then a low voltage of about ±2 Vis applied, thus varying the drain current in the MOS transistor Tr11finely. Therefore, in the neurocomputer of this embodiment, even if theload signal S₁ is at a relatively low voltage, it is possible to addweights at various levels corresponding to the voltage.

[0348] The synapse units of the neurocomputer of this embodiment has afunction of storing the history of the load signal S₁ as well as afunction of forgetting the history when not used for a long time.

[0349] The semiconductor device of the seventh embodiment including theferroelectric capacitor is used for the synapse unit in theneurocomputer of this embodiment. Alternatively, the semiconductordevice of the fifth embodiment including the dielectric capacitor or thesemiconductor devices of the eighth through eleventh embodiments may beused.

[0350] A semiconductor device according to the present invention is usedas a multilevel memory and is applicable to a neurocomputer including amultilevel memory.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor substrate; and a memory in which a first capacitor,including a first upper electrode, a first dielectric layer and a firstlower electrode and formed over the semiconductor substrate, and asecond capacitor, including a second upper electrode, a seconddielectric layer and a second lower electrode and formed over thesemiconductor substrate, are disposed, wherein the semiconductor devicecan store information with three or more levels, and wherein the firstand second dielectric layers have hysteresis characteristics exhibitingmutually differing coercive voltages.
 2. The semiconductor device ofclaim 1, wherein the first and second capacitors are polarized in onedirection during operation.
 3. The semiconductor device of claim 1,including a transistor including: a gate insulating film formed on thesemiconductor substrate; and a gate electrode formed on the gateinsulating film and made of a conductor film, wherein both of the firstand second lower electrodes are united with the gate electrode.
 4. Thesemiconductor device of claim 1, including: a gate insulating filmformed on the semiconductor substrate; and a gate electrode formed onthe gate insulating film and made of a conductor film, wherein each ofthe first and second lower electrodes is connected to the gateelectrode.
 5. The semiconductor device of claim 1, wherein in respectivefirst-half stages in ranges in which the polarizations of the first andsecond capacitors are from zero to saturation, the polarizations of thefirst and second capacitors vary at mutually different rates with changein voltage.
 6. The semiconductor device of claim 1, wherein each of thefirst and second dielectric layers includes a ferroelectric layer. 7.The semiconductor device of claim 1, wherein the first and second upperelectrodes are connected to each other.
 8. The semiconductor device ofclaim 3, wherein the first and second dielectric layers are formed outof an identical film.
 9. The semiconductor device of claim 8, whereinthe first and second dielectric layers are made of an identicalmaterial, and wherein the semiconductor device further includes aparaelectric capacitor connected in parallel with the first and secondcapacitors.
 10. The semiconductor device of claim 8, including acapacitor interposed between the second capacitor and the gateelectrode.
 11. The semiconductor device of claim 1, wherein the firstand second dielectric layers differ mutually in area.
 12. Thesemiconductor device of claim 1, wherein the first and second dielectriclayers are made of mutually different materials.
 13. The semiconductordevice of claim 1, wherein the first and second dielectric layers differmutually in thickness.
 14. The semiconductor device of claim 11, whereinthe area ratio between the electrodes of the first and secondcapacitors, i.e., (the area of the first capacitor)/(the area of thesecond capacitor), is in the range of 0.2 to 2, both inclusive.
 15. Thesemiconductor device of claim 12, wherein the area ratio between theelectrodes of the first and second capacitors, i.e., (the area of thefirst capacitor)/(the area of the second capacitor), is in the range of0.5 to 2, both inclusive.
 16. The semiconductor device of claim 1,including: an MIS transistor connected to the first and second upperelectrodes and including a gate electrode; a word line connected to thegate electrode of the MIS transistor; and a bit line connected to theMIS transistor.
 17. A semiconductor device, comprising: acontrol-voltage supply unit; a field-effect transistor including a gateelectrode having a function of accumulating a charge; and a capacitorand a resistor, disposed in parallel and interposed between thecontrol-voltage supply unit and the gate electrode, wherein thesemiconductor device can store multilevel information.
 18. Thesemiconductor device of claim 17, wherein a charge is injected from thecontrol-voltage supply unit into the gate electrode.
 19. Thesemiconductor device of claim 17, wherein the semiconductor devicefunctions as an analog memory in which multilevel information can bestored continuously according to the amount of the charge accumulated inthe gate electrode
 20. The semiconductor device of claim 17, wherein theresistor is made of a dielectric material.
 21. The semiconductor deviceof claim 17, wherein the control-voltage supply unit is as an upperelectrode, wherein the gate electrode of the field-effect transistor isconnected to an intermediate electrode, wherein the capacitor is adielectric capacitor including the upper electrode, the intermediateelectrode and a dielectric layer, the dielectric layer being interposedbetween the upper electrode and the intermediate electrode, and whereinthe dielectric layer has a resistance component functioning as theresistor.
 22. The semiconductor device of claim 20, wherein the resistorhas a resistance value that varies according to the strength of anelectric field applied to the resistor.
 23. The semiconductor device ofclaim 20, wherein the resistor has a resistance value which is almostconstant when the strength of an electric field applied to the resistoris at a level equal to or smaller than a given level and which decreaseswhen the strength of the electric field exceeds the given level.
 24. Thesemiconductor device of claim 20, wherein a pass current flowing throughthe resistor increases substantially in proportion to a voltage appliedto both ends of the resistor when the absolute value of the appliedvoltage is equal to or smaller than a given value, while the passcurrent increases exponentially when the absolute value of the appliedvoltage exceeds the given value.
 25. The semiconductor device of claim24, wherein a pass current flowing per unit area of the resistor is 100[mA/cm²] or less in a voltage range in which the pass current flowingthrough the resistor increases substantially in proportion to thevoltage.
 26. The semiconductor device of claim 20, wherein the capacitorincludes a ferroelectric layer, and wherein the resistor is made of aferroelectric material.
 27. The semiconductor device of claim 21,further including at least one resistor provided separately from thecapacitor.
 28. The semiconductor device of claim 27, wherein theresistor provided separately from the capacitor is a variable resistorthat includes an oxide containing an element selected from the groupconsisting of Ba, Sr, Ti, Zn, Fe and Cu, or includes an element selectedfrom the group consisting of SiC, Si and Se.
 29. The semiconductordevice of claim 27, wherein the resistors are diodes that are connectedin parallel and disposed in opposite orientations.
 30. The semiconductordevice of claim 27, further including an MIS transistor, wherein the MIStransistor has an ON resistance functioning as the resistor providedseparately from the capacitor.
 31. The semiconductor device of claim 27,wherein the resistor provided separately from the capacitor is avariable resistance element made of a variable resistance materialhaving a resistance value that varies depending on the crystallinity ofthe material.
 32. The semiconductor device of claim 17, wherein thesemiconductor device is used as a synapse unit in a neurocomputer.
 33. Amethod for driving a semiconductor device including a control-voltagesupply unit, a field-effect transistor including a gate electrode havinga function of accumulating a charge, a capacitor, and a resistor, thecapacitor and the resistor being disposed in parallel and interposedbetween the control-voltage supply unit and the gate electrode, themethod comprising the steps of: a) applying a write voltage to both endsof the resistor to vary the amount of the charge accumulated in the gateelectrode via the resistor, thereby changing a threshold voltage of thefield-effect transistor; and b) reading out information according tovariation in a drain current in the field-effect transistor.
 34. Themethod of claim 33, wherein the capacitor includes a dielectric layer.35. The method of claim 34, wherein in the step a), a pass currentflowing through the resistor increases substantially in proportion tothe write voltage when the absolute value of the write voltage is equalto or smaller than a give value, and wherein the pass current increasesexponentially as the write voltage increases, when the absolute value ofthe write voltage exceeds the given value.
 36. The method of claim 35,wherein in the step a), when the absolute value of the write voltage isequal to or smaller than the given value, the amount of the chargeaccumulated in the gate electrode is controlled depending on the lengthof a time period over which the write voltage is applied.
 37. The methodof claim 35, wherein in the step a), when the absolute value of thewrite voltage is equal to or smaller than the given value, a passcurrent flowing per unit area of the resistor is 100 [mA/cm²] or less.38. The method of claim 35, wherein in the step a), when the absolutevalue of the write voltage exceeds the given value, the write voltage isset to have an uniform pulse width and the amount of the chargeaccumulated in the gate electrode is controlled depending on themagnitude of the absolute value of the write voltage.
 39. The method ofclaim 38, wherein in the step a), when the absolute value of the writevoltage exceeds the given value, the amount of the charge accumulated inthe gate electrode is subjected to a coarse control, and when theabsolute value of the write voltage is lower than the give value, theamount of the charge accumulated in the gate electrode is subjected to afine control.
 40. The method of claim 33, wherein in the step a), thewrite voltage is in positive- and negative-voltage ranges that extend toan identical absolute value.